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@ =z ;%A _@         Microsoft C/C++ program database 2.00 JGMicrosoft C/C++ MSF 7.00 DS Fcb = %d rsvfunctab/names A?; @ =z ;%A _@vfunctab A?; @ =z ;%A _@vfunctab A?; @ =z ;%A _@* Portable PDB *#Pdb#~#GUID#BlobMethod.#%XCOM+_Entry_Point/LinkInfovfunctab A?; @ =z ;%A _@__enc$textbss$begin__enc$textbss$endrcbrc' line %d) ('v1^FE?^IE-v% \TD 0hKF{'0vfunctab A?; @ =z ;%A _@%d%s (ordinal)'%s'!'%s'Microsoft (R) LINKvfunctab 18 A?; @ =z ;%A _@Cannot access 32-bit type pool with 16-bit APIs_NT_ALT_SYMBOL_PATH_NT_SYMBOL_PATHSystemRoot.dbgsymbols\SRV*SYMSRV*CACHE*Software\Microsoft\VisualStudio\MSPDBSymbolSearchPathSYMSRV.DLLSymbolServerWSymbolServerSetOptionsSymbolServerStoreFileWSYMSRV.DLL*0w,aQ mjp5c飕d2yҗ+L |~-d jHqA}mQDžӃVlkdzbeO\lcc=  n;^iLA`rqgjm Zjz  ' }Dңhi]Wbgeq6lknv+ӉZzJgo߹ﾎCՎ`~ѡ8ROggW?K6H+ L J6`zA`Ugn1yiFafo%6hRw G "/&U;( Z+j\1е,[d&c윣ju m ?6grWJz+{8 Ғ |! ӆBhn[&wowGZpj;f\ eibkaElx TN³9a&g`MGiIwn>JjѮZf @;7SŞϲG0򽽊º0S$6к)WTg#.zfJah]+o*7 Z-/src/headerblock/src/files/vfunctabvfunctab A?; @ =z ;%A _@%08x.Base@ILT+%d(+%d)vfunctab A?; @ =z ;%A _@::::__unnamedvfunctab A?; @ =z ;%A _@}{oK\z%`Q}Z,GDTyOC7ҹ84_$lAe ؉ضF could not get live range length for variable from PDB // could not get variable index ID from PDB "%.*s\b\t\r\n\\.voidboolintuintbytefloatstringBufferTextureTexture1DTexture1DArrayTexture2DTexture2DMSTexture2DArrayTexture2DMSArrayTexture3DTextureCubeTextureCubeArraysamplerSamplerStatesampler1Dsampler2Dsampler3DsamplerCUBEPixelShaderVertexShaderGeometryShaderHullShaderDomainShaderRasterizerStateDepthStencilStateBlendStateRenderTargetViewDepthStencilViewpixelfragmentvertexfragmentinterfaceComputeShaderdoublemin8floatmin10floatmin16floatmin12intmin16intmin16uintUNKNOWN // %s%s%urow_major %s%ux%u%s%ux%ustruct %s struct { // Offset: %4u // }%s %s %s[%u];mixedunormsnormsint// Buffer Definitions: cbuffertbufferinterfacesResource bind info for// %s %s // { // Offset: N/A Size: N/A [unused] [unused]// Offset: %4u Size: %5u%s // = 0x%08x Textures: t%u-t%uTexture: t%u, Samplers: s%u-s%uSampler: s%u// } // Resource Bindings: // Name Type Format Dim HLSL Bind Count // ------------------------------ ---------- ------- ----------- -------------- ------ // Name Type Format Dim ID HLSL Bind Count // ------------------------------ ---------- ------- ----------- ------- -------------- ------ cbCBtTtextureUAVuUsSsampler_cbugBUGNAbuf1d2d3dcubecubearray1darray2darray%sMS%d%sMSr/ostructr/wr/w+cntappendconsume%s%u,space%u%uunbounded// %-30s %10s %6s%d %11s %14s %6s %s // %-30s %10s %7s %11s %14s %6s %s // %-30s %10s %6s%d %11s %7s %14s %6s %s // %-30s %10s %7s %11s %7s %14s %6s %s // Constant buffer to DX9 shader constant mappings: // Target Reg Buffer Source Reg Component // ---------- ------- ---------- --------- // b%-9d cb%-5d %10d %9d // i%-9d cb%-5d %10d %9d // Target Reg Buffer Start Reg # of Regs Data Conversion // ---------- ------- --------- --------- ---------------------- // clip%-6d cb%-5d %9d %9d (// c%-9d cb%-5d %9d %9d ( FLTBOOL INTUINTUNKN,) // Runtime generated constant mappings: // Target Reg Constant Description // ---------- -------------------------------------------------- Vertex Shader position offsetInstance IDUnknown Value// c%-10d %49s // Sampler/Resource to DX9 shader sampler mappings: // Target Sampler Source Sampler Source Resource // -------------- --------------- ---------------- // s%-13d s%-14d t%-16d // Approximately %i instruction slots used UndefinedIsolineTriangleQuadrilateral// Tessellation Domain # of control points // -------------------- -------------------- // %-20s %20u PointLineClockwise TrianglesCounter-Clockwise TrianglesIntegerInteger Power of 2Odd FractionalEven Fractional// Tessellation Output Primitive Partitioning Type // ------------------------------ ------------------ // %-30s %-18s // %s signature: // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------- ------ // no %s m%u:%-17s%-20s %5uSV_Depth N/A oDepthSV_DepthGreaterEqual oDepthGESV_DepthLessEqual oDepthLESV_Coverage oMaskSV_StencilRef oStencilRef primID special %c%c%c%c %8uNONECLIPDSTCULLDSTPOSRTINDEXVPINDEXVERTIDPRIMIDINSTIDFFACESAMPLETARGETDEPTHDEPTHGEDEPTHLECOVERAGEINNERCOVSTENCILREFQUADEDGEQUADINTTRIEDGETRIINTLINEDETLINEDEN %8sunknownmin2_8fmin16fmin16imin16u %7s YES NOxyzwyesno// Function parameter signature (return: %s, parameters: %u): // Name SemanticName In 1st,Num,Mask Out 1st,Num,Mask Type // -------------------- -------------------- --------------- ---------------- ------------------------------ // %-20s v%-4u %-3u %c %*s o%-4u %-3u inout in out row_major void bool float min16float min10float int min16int min12int uint min16uint min8uint%ux%u%s%s%s%d%s%s%d r c v of ob oi ip l[%s%d[%s].%c][%s%d.%c] (%.9g, %.9g) oC expr vPos vPSize%f0x%08x%d+#INF-#INF#NaN%.14fl0x%016I64xUI64%4u%c 0x%08X: // approximately %u instruction%s used Error: Texture shader assembly not found!Error: Error getting texture shader literal block. tx_%u_%u xyzwdef32 { as { nonuniform }r%uv%uc%ua%ut%uoPosoPtsoFogoX%uoD%uoT%uo%ui%uoC%uoDepths%ub%uaLvPosvFacem%ul%up%ux%u[] ; // Generated by Microsoft (R) D3DX9 Shader Disassembler // Parameters: // Registers: // Name Reg Size - ----- ---- %c%-4u %4u// Default values: // %s // %c%-4u= { %g, %g, %g, %g }{ %d, %d, %d, %d }truefalservoldmicblabelvPrimoDepthGEoDepthLEnullrasterizeroMaskoStencilReffbftfpivovvOutputControlPointIDvForkInstanceIDvJoinInstanceIDvicpvocpvpcvDomainthisgvThreadIDvThreadGroupIDvThreadIDInGroupvThreadIDInGroupFlattenedvCoveragevInnerCoveragevGSInstanceIDvCycleCounter=|[%d]%d[%d]._%d_%d.%d. + %d]((%f)(%fl, %fl)(%f, %f, %f, %f)(0x%08x)(%d)undefinedclip_distancecull_distancepositionrendertarget_array_indexviewport_array_indexvertex_idsampleIndexprimitive_idinstance_idis_front_facefinalQuadUeq0EdgeTessFactorfinalQuadVeq0EdgeTessFactorfinalQuadUeq1EdgeTessFactorfinalQuadVeq1EdgeTessFactorfinalQuadUInsideTessFactorfinalQuadVInsideTessFactorfinalTriUeq0EdgeTessFactorfinalTriVeq0EdgeTessFactorfinalTriWeq0EdgeTessFactorfinalTriInsideTessFactorfinalLineDetailTessFactorfinalLineDensityTessFactor preshader vs_2_x lib_4_0_vs_2_x vs_2_sw vs_3_sw ps_2_x lib_4_0_ps_2_x ps_2_sw ps_3_sw vs_%u_%u lib_4_0_vs_%u_%u ps_%u_%u lib_4_0_ps_%u_%u // disassembly only available for VS and PS targets Error: unexpected end of buffer // %s #line %u "%s" %u + !) dcldefdefidefbnopmovmovaaddsubmadmulrcprsqdp3dp4minmaxsltsgedstabspowcrssgnnrmexpplogpcndcmpsetpsincossincostrunclitlrpm4x4m4x3m3x4m3x3m3x2callcallnzloopretendlooprependrepifelseendifbreaktexkilltexbemtexbemltexreg2artexreg2gbtexreg2rgbtexldltexlddtexm3x2padtexm3x2textexm3x3padtexm3x3textexm3x3spectexm3x3vspectexm3x2depthtexm3x3texdp3textexdp3texdepthbemdp2adddsxdsyreserved0phaseexplogfrctexldptexldbtexldtextexcrdtexcoord???_2d_cube_volume_unknown_position_blendweight_blendindices_normal_psize_texcoord_tangent_binormal_tessfactor_positiont_color_fog_depth_sample_gt_eq_ge_lt_ne_le_x8_x4_x2_d2_d4_d8_sat_pp_centroid%.9g1-_bias_bx2_dz_dw_abs // ,%d>, %s::::%s<%d>// approximately %u instruction slot%s used (%u texture, %u arithmetic)// unable to iterate instruction in PDB // incorrect instruction offset in debug info // incorrect token offset in debug info // incorrect file offset in debug info // file name too long in debug info // unable to find instruction in PDB // unable to get statement flag from PDB // unable to instruction offset from PDB // unable to get file id from PDB // unable to get line number from PDB // unable to get column number from PDB // unable to get source file info from PDB // unable to get file name from PDB // line mismatch in debug info // column mismatch in debug info // filename length mismatch in debug info // filename mismatch in debug info : :[%uu:NaNInf%gf // incorrect instruction offset in debug info // too many instruction outputs in debug info // incorrect scalar offset in debug info // incorrect variable offset in debug info // incorrect token offset in debug info %s[r%u.%c]<%s[r%u.%c/%u]<%s<// unable to get typedef type from PDB // unable to get type length from PDB // offset overruns length for type in PDB // unable to get sub-variable type from PDB // could not get UDT children in PDB // could not get find UDT child with correct offset in PDB // could not get UDT child offset in PDB // could not get UDT child type in PDB // could not get UDT child length in PDB .%S// unable to get array element type from PDB // could not get array element stride from PDB // unable to get vector element type from PDB // could not get vector element length from PDB // could not get vector length from PDB // invalid vector member .%c// unable to get matrix element type from PDB // could not get matrix element length from PDB // could not get matrix columns from PDB // could not get matrix rows from PDB // could not get matrix row-major flag from PDB // could not get matrix major stride from PDB // invalid matrix member ._m%u%u// unable to get HLSL type kind from PDB // unexpected data kind in PDB %s[%u][%u].%c%s%u.%c%s[%u].%c// unexpected register type in PDB // could not get location type from PDB // could not get register type from PDB // could not get register index count from PDB // could not get register index values from PDB // // unexpected location type in PDB unable to get variable name from PDB <- %S unable to get variable subfield offset from PDB unable to get variable type from PDB // could not find inner most frame in PDB // Initial variable locations:; Prior locations: Post-call locations: //buffertexture1dtexture2dtexture2dmstexture3dtexturecubetexture1darraytexture2darraytexture2dmsarraytexturecubearrayraw_bufferstructured_buffer_glc_opc_rov%s%u[%u:%u]*]refactoringAllowedenableDoublePrecisionFloatOpsenableRawAndStructuredBuffersforceEarlyDepthStencilskipOptimizationenableMinimumPrecisionenable11_1DoubleExtensionsenable11_1ShaderExtensionsallResourcesBound[%8I64u] _aoffimmi_indexable [precise(%i,%i,%i), stride=%u_rcpfloat _uint _uglobal_ugroup_g_t x%i[%i], %d %i | none pointlist linestrip trianglestrip undefined ??? %u point line triangle lineadj triangleadj patch1 patch2 patch3 patch4 patch5 patch6 patch7 patch8 patch9 patch10 patch11 patch12 patch13 patch14 patch15 patch16 patch17 patch18 patch19 patch20 patch21 patch22 patch23 patch24 patch25 patch26 patch27 patch28 patch29 patch30 patch31 patch32 constant linear linear centroid linear noperspective linear noperspective centroid linear sample linear noperspective sample CB%d[%d:%d]CB%d, dynamicIndexed, immediateIndexed, space=%d %d_%s domain_quad domain_tri domain_isoline ??? partitioning_integer partitioning_pow2 partitioning_fractional_odd partitioning_fractional_even output_point output_line output_triangle_cw output_triangle_ccw l(%f)_z _nz dcl_immediateConstantBuffer { { , }printf errorf "%s"// COMMENT: %sundecipherable custom data_dynamicindexed fp%u[%u][%u] = {, ft%uft%u ft%u = {, fb%ufb%u, %u, %u, %u %u, %u, %u, mode_default, mode_comparison, mode_mono, space=%ups_%d_%d vs_%d_%d hs_%d_%d ds_%d_%d gs_%d_%d cs_%d_%d lib_%d_%d // Available Class Types: // Name ID CB Stride Texture Sampler // ------------------------------ ---- --------- ------- ------- // %-30s %4u %9u %7u %7u // Available Class Instances: // Name Type CB CB Offset Texture Sampler // --------------------------- ---- -- --------- ------- ------- %s[%u]// %-27s %4u %2u %9u - - %7u - %7u - // Interface slots, %u total: // Slots // +----------+---------+--------------------------------------- // | Type ID |%4u-%-4u|// | Type ID |%4u |// | Type ID | |%-5u // | Table ID | |// %s shader bytecode: %s Microsoft (R) D3D Shader Disassembler // Note: SHADER WILL ONLY WORK WITH THE DEBUG SDK LAYER ENABLED. // Note: shader requires additional functionality: // %s Patch ConstantInputOutput// Debug name: %s // Pixel Shader runs at sample frequency Level9XNA PrepassXNAD3DCOMPILER_DISASSEMBLY_FORCE_HEX_LITERALS
//
// Library:  flags %x, %u functions:
// %3u  %s
//
// Created by:  %s
//
// Trace has %u steps (some may be inactive)

%4u: Illegal instruction index
%s %s = %s %s[%d] = 
{

    asm {


    },
asm {


}
    NULL,
NULL;

technique10 
{
    pass 
    {
        // No embedded %s
        %s = %s[%d];
        %s = %s;
        %s = asm {


};        %s = NULL;
    }
}

xyzw5aueMvaa9<_ynHE#=FALSETRUEZEROALLWIREFRAMESOLIDMIN_MAG_MIP_POINTMIN_MAG_POINT_MIP_LINEARMIN_POINT_MAG_LINEAR_MIP_POINTMIN_POINT_MAG_MIP_LINEARMIN_LINEAR_MAG_MIP_POINTMIN_LINEAR_MAG_POINT_MIP_LINEARMIN_MAG_LINEAR_MIP_POINTMIN_MAG_MIP_LINEARANISOTROPICCOMPARISON_MIN_MAG_MIP_POINTCOMPARISON_MIN_MAG_POINT_MIP_LINEARCOMPARISON_MIN_POINT_MAG_LINEAR_MIP_POINTCOMPARISON_MIN_POINT_MAG_MIP_LINEARCOMPARISON_MIN_LINEAR_MAG_MIP_POINTCOMPARISON_MIN_LINEAR_MAG_POINT_MIP_LINEARCOMPARISON_MIN_MAG_LINEAR_MIP_POINTCOMPARISON_MIN_MAG_MIP_LINEARCOMPARISON_ANISOTROPICTEXT_1BITONESRC_COLORINV_SRC_COLORSRC_ALPHAINV_SRC_ALPHADEST_ALPHAINV_DEST_ALPHADEST_COLORINV_DEST_COLORSRC_ALPHA_SATBLEND_FACTORINV_BLEND_FACTORSRC1_COLORINV_SRC1_COLORSRC1_ALPHAINV_SRC1_ALPHACLAMPWRAPMIRRORBORDERMIRROR_ONCEFRONTBACKNEVERLESSEQUALLESS_EQUALGREATERNOT_EQUALGREATER_EQUALALWAYSKEEPREPLACEINCR_SATDECR_SATINVERTINCRDECRADDSUBTRACTREV_SUBTRACTMINMAXGenerateMipsDS_StencilRefAB_BlendFactorAB_SampleMaskFillModeCullModeFrontCounterClockwiseDepthBiasDepthBiasClampSlopeScaledDepthBiasDepthClipEnableScissorEnableMultisampleEnableAntialiasedLineEnableDepthEnableDepthWriteMaskDepthFuncStencilEnableStencilReadMaskStencilWriteMaskFrontFaceStencilFailFrontFaceStencilDepthFailFrontFaceStencilPassFrontFaceStencilFuncBackFaceStencilFailBackFaceStencilDepthFailBackFaceStencilPassBackFaceStencilFuncAlphaToCoverageEnableBlendEnableSrcBlendDestBlendBlendOpSrcBlendAlphaDestBlendAlphaBlendOpAlphaRenderTargetWriteMaskFilterAddressUAddressVAddressWMipLODBiasMaxAnisotropyComparisonFuncBorderColorMinLODMaxLOD[%s[%u + %s].%c][%s[%s].%c][%s[%u].%c][%s.%c]%s[%u + (Error: Effects expression assembly in invalid format!Error: Effects expression assembly not found!Error: Error getting Effects expression constant table.Error: Error getting Effects expression literal block. /* ##Internal error##0x%02x */%s  = {  =  : %s : packoffset(c%u.%c) : register(%c%u) = { "%s", "%s" = "%s"<
// Offset: %4u, size: %4u
// %u %s buffer(s)
single asm {
/* Stream %u out decl: "%s" *//* Stream %u to rasterizer *//* Interface parameter %u bound to: %s%s[%s[%s]%s[eval()]eval(/* Stream out decl: "%s" */
{,
// %u %s object(s)
// %u %s interface(s)
// %u technique(s)
technique11technique10pass

// %u groups(s)
fxgroup// FX Version: %s
// Child effect (requires effect pool): %s
localsharedfx_4_0fx_4_1fx_5_0ID3D11FunctionLinkingGraph::CreateModuleInstance: FLG module instance has already been createdID3D11FunctionLinkingGraph::CreateModuleInstance: NULL parameterID3D11FunctionLinkingGraph::CreateModuleInstance: FLG has no nodesID3D11FunctionLinkingGraph::CreateModuleInstance: uninitialized shader output signature parameter #%u, component '%c'ID3D11FunctionLinkingGraph::CreateModuleInstance: uninitialized parameter #%u component '%c' passed to function '%s::%s' at call site #%uID3D11FunctionLinkingGraph::SetSignature: illegal name for parameter %u__%s_n%u_%uID3D11FunctionLinkingGraph::SetSignature: illegal semantic name for parameter %uID3D11FunctionLinkingGraph::SetSignature: unknown class for parameter %uID3D11FunctionLinkingGraph::SetSignature: NumRows must be between 1 and 4 for parameter %uID3D11FunctionLinkingGraph::SetSignature: NumColums must be between 1 and 4 for parameter %uID3D11FunctionLinkingGraph::SetSignature: illegal type for parameter %uID3D11FunctionLinkingGraph::SetSignature: unknown interpolation mode for parameter %uID3D11FunctionLinkingGraph::SetInputSignature: NULL parameterID3D11FunctionLinkingGraph::SetInputSignature: too many parameters (%u) in the input signature (max=%u)ID3D11FunctionLinkingGraph::SetInputSignature: input signature has already been setID3D11FunctionLinkingGraph::SetInputSignature: input signature must be the first FLG nodeID3D11FunctionLinkingGraph::SetInputSignature: input signature has duplicate parameter names/semanticsID3D11FunctionLinkingGraph::SetOutputSignature: NULL parameterID3D11FunctionLinkingGraph::SetOutputSignature: too many parameters (%u) in the output signature (max=%u)ID3D11FunctionLinkingGraph::SetOutputSignature: output signature must be the last FLG nodeID3D11FunctionLinkingGraph::SetOutputSignature: output signature has already been specifiedID3D11FunctionLinkingGraph::SetOutputSignature: output signature has duplicate parameter names/semanticsID3D11FunctionLinkingGraph::SetOutputSignature: input and output signatures have duplicate parameter namesID3D11FunctionLinkingGraph::CallFunction: NULL parameterID3D11FunctionLinkingGraph::CallFunction: a function cannot be called after the output signature has been setID3D11FunctionLinkingGraph::CallFunction: function name cannot be emptyID3D11FunctionLinkingGraph::CallFunction: function '%s' prototype is not found in the moduleID3D11FunctionLinkingGraph::CallFunction: function '%s' input parameter %u has unsupported register mappingID3D11FunctionLinkingGraph::CallFunction: function '%s' output parameter %u has unsupported register mappingID3D11FunctionLinkingGraph::CallFunction: %s::%s function has non-matching prototypes (different parameter counts)ID3D11FunctionLinkingGraph::CallFunction: %s::%s function has non-matching prototypes (parameter %u)ID3D11FunctionLinkingGraph::PassValueWithSwizzle: illegal character in the swizzle string '%s'sourcedestinationID3D11FunctionLinkingGraph::PassValueWithSwizzle: %s parameter component '%c' is not definedID3D11FunctionLinkingGraph::PassValueWithSwizzle: destination swizzle '%s' cannot have replicated componentsID3D11FunctionLinkingGraph::PassValueWithSwizzle: swizzle string cannot be emptyID3D11FunctionLinkingGraph::PassValueWithSwizzle: NULL parameterID3D11FunctionLinkingGraph::PassValueWithSwizzle: source node must preceed destination node in FLGID3D11FunctionLinkingGraph::PassValueWithSwizzle: bad source swizzle '%s'ID3D11FunctionLinkingGraph::PassValueWithSwizzle: bad destination swizzle '%s'ID3D11FunctionLinkingGraph::PassValueWithSwizzle: illegal source parameter indexID3D11FunctionLinkingGraph::PassValueWithSwizzle: illegal destination parameter indexID3D11FunctionLinkingGraph::PassValueWithSwizzle: source parameter must be an INOUT or OUT parameterID3D11FunctionLinkingGraph::PassValueWithSwizzle: destination parameter must be an INOUT or IN parameterID3D11FunctionLinkingGraph::PassValueWithSwizzle: value must be produced by an output parameterID3D11FunctionLinkingGraph::PassValueWithSwizzle: value must be consumed by an input parameterID3D11FunctionLinkingGraph::PassValueWithSwizzle: cannot pass values for parameters of type voidID3D11FunctionLinkingGraph::PassValueWithSwizzle: incompatible element typesID3D11FunctionLinkingGraph::PassValueWithSwizzle: possible loss of precision when passing value from <%u, %d> to <%u, %d> ()ID3D11FunctionLinkingGraph::PassValueWithSwizzle: incompatible row dimensionsID3D11FunctionLinkingGraph::PassValueWithSwizzle: incompatible type classesID3D11FunctionLinkingGraph::PassValueWithSwizzle: incompatible column dimensionsID3D11FunctionLinkingGraph::PassValueWithSwizzle: swizzle is not supported for matricesID3D11FunctionLinkingGraph::PassValueWithSwizzle: source value has too few componentsID3D11FunctionLinkingGraph::PassValueWithSwizzle: destination parameter component '%c' has already been initializedrow_major min8uintinout in out nointerpolation centroid noperspective noperspective centroid sample noperspective sample  %s_%s_n%u_%u%s_n%u_%uvoid main()
{
}
namespace %s
{    
 %s();
}

void main(%s("AB4SV_VertexIDSV_InstanceIDSV_PositionSV_PrimitiveIDSV_SampleIndexSV_IsFrontFaceSV_RenderTargetArrayIndexSV_ClipDistanceSV_CullDistanceSV_TargetID3D11Linker::SetEntry: entry cannot be NULLID3D11Linker::SetEntry: shader target name cannot be NULLID3D11Linker::Link: NULL parameterID3D11Linker::SetEntry: entry has already been setID3D11Linker::SetEntry: unsupported shader target '%s'ID3D11Linker::SetEntry: only FLG and cs_5_0 entries are supported currentlyID3D11Linker::Link: failed to generate byte codeID3D11Linker::Link: function '%s::%s' is not found in registered module instancesID3D11Linker::Link: function '%s::%s' prototype does not match function signatureID3D11Linker::Link: function '%s::%s' prototype and signature semantics do not match for parameter %uID3D11Linker::Link: function '%s::%s' prototype and signature flags do not match for parameter %uID3D11Linker::Link: function '%s::%s' prototype and signature types do not match for parameter %uID3D11Linker::Link: function '%s::%s' is missing a legacy shader blob necessary to link '%s' targetID3D11Linker::Link: function '%s::%s' legacy byte code (version '%u.%u') cannot be used to link shader target '%s'ID3D11Linker::Link: remapping has not been specified for cbuffer slot %u in function '%s::%s'ID3D11Linker::Link: cbuffer slot %u in function '%s::%s' maps to real slot %u that is too big (max=%u)ID3D11Linker::Link: illegal remapping specified for sampler slot range [%u, %u] in function '%s::%s'ID3D11Linker::Link: illegal remapping specified for resource slot range [%u, %u] in function '%s::%s'ID3D11Linker::Link: illegal remapping specified for UAV slot range [%u, %u] in function '%s::%s'ID3D11Linker::Link: a duplicate resource names (%s) are not allowed (use namespaces to disambiguate)ID3D11Linker::Link: function '%s::%s' byte code (version '%u.%u') cannot be used for the requested shader target '%s'ID3D11Linker::Link: several virtual samplers with incompatible sampler modes map to slot %uID3D11Linker::Link: remapping of resource (slot %u) to UAV (slot %u) in function '%s::%s' is allowed only for buffersresourceID3D11Linker::Link: several virtual resources with incompatible properties map to real %s slot %uID3D11Linker::Link: several UAVs/SRVs with incompatible properties map to slot %uID3D11Linker::Link: cbuffer (size=%u) remapping -> in function '%s::%s' exceeds the maximum cbuffer size (%u)ID3D11Linker::Link: immediate cbuffer (%u entries) exceeds the limit of %u entriesID3D11Linker::Link: not enough temporary registers (max=%u).ID3D11Linker::Link: total number of registers %u exceeds %u.inputoutputID3D11Linker::Link: bad %s semantic name '%s'ID3D11Linker::Link: %s sematic %s number must be in range [%u, %u] for shader target '%s'ID3D11Linker::Link: invalid %s SV_ semantic '%s' for shader target '%s'ID3D11Linker::Link: invalid type specified for %s semantic '%s'ID3D11Linker::Link: %s semantic '%s' can only have one row and number of components between [%u,%u]ID3D11Linker::Link: invalid interpolation mode specified for %s semantic '%s'ID3D11Linker::Link: integer types must have constant interpolation mode for %s semantic '%s'ID3D11Linker::Link: invalid class specified for %s semantic '%s'ID3D11Linker::Link: only one Depth sematic can be spesified for shader target '%s'ID3D11Linker::Link: pixel shaders cannot declare arbitrary output semantics ('%s')ID3D11Linker::Link: SV_ClipDistance semantics cannot be used when using the clipplanes attributeID3D11Linker::Link: overlapping %s sematics %s are not supportedID3D11Linker::Link: Cannot use clipplanes attribute without specifying a 4-component SV_Position outputID3D11Linker::Link: clipplanes can only specified for Vertex shadersID3D11Linker::Link: SV_ClipDistance and SV_CullDistance occupy %u %s registers, only two are allowedID3D11Linker::Link: failed to pack %s signatureID3D11Linker::Link: all components of %s semantic '%s' must be initialized by '%s' shadersID3D11Linker::Link: SV_Target outputs must be contiguous from SV_Target0 to SV_TargetN for shader target '%s'ID3D11Linker::Link: the number of sample entries exceeded the limit of %uID3D11Linker::Link: input semantic '%s' cannot be read by '%s' shadersID3D11Linker::Link: output semantic '%s' cannot be written by '%s' shadersID3D11Linker::Link: the shader requires %u defc constants, which exceeds the allowed limit of %uID3D11Linker::Link: the shader requires %u defb constants, which exceeds the allowed limit of %uID3D11Linker::Link: the shader requires %u defi constants, which exceeds the allowed limit of %uID3D11Linker::UseLibraryWithNamespace: NULL parameterID3D11Linker::AddClipPlaneFromCBuffer: cbuffer slot index is too large (max=%u)ID3D11Linker::AddClipPlaneFromCBuffer: cbuffer entry index is too large (max=%u)ID3D11Linker::AddClipPlaneFromCBuffer: clipplane for cbuffer %u entry %u has already been specifiedID3D11Linker::AddClipPlaneFromCBuffer: the maximum allowed number of clipplane fron a cbuffer is %uMicrosoft (R) Shader Linker$CBufferForClipPlane_%uID3D11Linker::Link: failed to remap SRV to UAV (slot=%u)ID3D11Linker::Link: remapping has not been specified for resource slot %uID3D11Linker::Link: remapping of resource (slot %u) to UAV (slot %u) is allowed only for buffersID3D11Linker::Link: resource slot %u maps to real resource slot %u that is too big (max=%u)ID3D11Linker::Link: resource slot %u maps to real UAV slot %u that is too big (max=%u)ID3D11Linker::Link: remapping has not been specified for UAV slot %uID3D11Linker::Link: UAV slot %u maps to real slot %u that is too big (max=%u)vs_4_0vs_4_0_level_9_1vs_4_0_level_9_3vs_4_1vs_5_0ps_4_0ps_4_0_level_9_1ps_4_0_level_9_3ps_4_1ps_5_0cs_5_0ID3D11Linker::Link: validation error:  %sFZHhx]00000 DDDDDDDDDDHHHHHHHH@@    2 2  
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@p		@@ @p	@ @p	@0@`		00@`	0@`	0Derivative being used before it was defined. consider moving the derivative assignment earlier in the program.Derivative is not defined in a different branch of flow-control. Consider moving the derivative assignment before any flow control statements.this operation"%s" with respect to "%s"this operation with respect to %sUnable to calculate derivative of %s. %sRedefinition of derivative, derivatives may only be assigned once.Derivatives of known values are unimplemented.Consider using the [unroll] attribute on the loop statement or using the assignment syntax to calculate it yourself (e.g.: x`(y) = z)Consider using the [flatten] attribute on the switch statement or using the assignment syntax to calculate it yourself (e.g.: x`(y) = z)Consider using the [flatten] attribute on the if statement or using the assignment syntax to calculate it yourself (e.g.: x`(y) = z)Consider using the assignment syntax to calculate it yourself (e.g.: x`(y) = z)5a0`
0
`Y0`0	[@0	b@p	@0	Bp	D0	[@0	b@`	@0	B`	D0	@@0	@:@@*@5@P@0	"0	@@0	@:@p@p*@5@0@0	"@p@p@0@@0	@pQ@0	"0	@@0	@@P@0	"0	@p@0	@p@0@0	"p0	@@@@0	"0	@p@@p@0	"p0	@0	@P @0	"P0	@0	@0 @0	"00	@0	@@@ @p	@p	@0	"0	@0	@@@P @p	@p	@0	"P0	@0	@@@p @`	@`	@0	"p0	@0	@@@0 @`	@`	@0	"0 
@0	@0	0	@@0	0	@P@0	P0	@@0	0	@@0	yp@0@0	@@p@0	Pp@@0@0	@:@2@5@p@0	Pp@@0@0	@:@2@p@0	@ @0	@@p@0	00@0	@p @0	 @0	@0	0	@@@@@0	0	@@p@@p@0	@0	@@p@0	p@0	@@p@0	@0	@p@p@0	0	@0	@0	@@@p@p@0	0	@0	0	@@0	0	@@0	0	@0	 0	@0	%s semantic '%s'IEEE-safe mode clamps float literals to 32-bit values, %g is losing precision (this warning will only be shown once per compile)32-bit floating-point operations flush denorm float literals to zero, %g is losing precision (this warning will only be shown once per compile)(unknown)ccmctcrapiqkjciclchcoicexraxraixraoixrxrxoxxixiptrpdrfclfcblstbtstiutubusgbgsinternal error: not all rules initializedinternal error: Rule class id invalid$Globals$Params$ThisPointer[internal error]Semantic length is limited to %d charactersZero character semantics aren't allowedVFaceSV_PrimitiveIdSV_OutputControlPointIDSV_DomainLocationSV_TessFactorSV_InsideTessFactorSV_DispatchThreadIDSV_GroupThreadIDSV_GroupIDSV_GroupIndexSV_InnerCoverageSV_GSInstanceIDSV_InstanceIdPositioncannot bind the same variable to multiple constants in the same constant bankthe size of constant buffer %s is %d 16-byte entries, which exceeds maximum allowed size of %d entriesreduce literal lit instruction <| Explicitsymmetric cmp <| Explicitreduce mov instruction <| Explicitmin of known positive identity <| Explicitmax of known positive identity <| Explicitlt of known range reduction <| Explicitge of known range reduction <| Explicitatan of known 0 or 1 identity <| Explicitmul of a half times add of same value identity <| Explicitnegative bool less then another bool identity <| Explicitbool multiply chain reduction <| Explicitdot of partial nullity reduction <| Expliciteval mul <| Explicitmin(x,y) where range of one is <= the other (ieee safe version) <| Explicitmax(x,y) where range of one is >= the other (ieee safe version) <| Explicitcmp of negated bool identity <| Explicitcmp diff to basic logic identity <| ExplicitNegative values for cmp and clip can be rordered <| ExplicitNegative value compared with zero <| ExplicitSequence of compares <| ExplicitFRC of add with integer can bypass add <| ExplicitMulitply by 1 reduces to no-op move <| ExplicitMultiply by -1 reduces to NEG operation <| Explicitinteger add sequence simplification <| Explicitinteger multiply by one identity <| Explicitinteger multiply by zero identity <| Explicitinteger multiply by negative one identity <| Explicitinteger multiply by literal identity <| Explicitshift of commutative literals <| Explicitcombine of commutative literals <| Explicitshift of commutative inputs <| Explicitimin(x,y) where one is <= the other <| Explicitimax(x,y) where one is >= the other <| Explicitumin(x,y) where one is <= the other <| Explicitumax(x,y) where one is >= the other <| Explicitumod(x,y) where x < y <| ExplicitEval range add inf flag if range not bound <| ExplicitEval range add NaN flag if integer mask says it's possible <| Explicitpropagate range info through mov <| Explicitpropagate special floating point values through div <| Explicitpropagate special floating point values through log <| Explicitpropagate special floating point values through add <| Explicitpropagate special floating point values through mul <| Explicitpropagate special floating point values through rsq <| Explicitpropagate special floating point values through rcp <| Explicitpropagate special floating point values through sqrt <| Explicitpropagate special floating point values through asin <| Explicitpropagate special floating point values through atan2 <| Explicit(A + L2) - (A + L1) = L2 - L1 if A non-NaN/Inf <| ExplicitDon't truncate double values to floats <| ExplicitDon't flush denorm values to zero <| ExplicitLiteral in Log * Mul * Exp pattern <| ExplicitAddition of same argument is same as multiply by 2 <| ExplicitMultiply by 2, 4, or 8 <| ExplicitMultiply by 0 reduces to literal 0 <| ExplicitA * (1/A) = 1 <| Explicitrange sequence reduction <| ExplicitKnown literals reduced to mov <| Explicitrsq result can be assumed positive <| Explicitmin(x,y) where range of one is <= the other <| Explicitmax(x,y) where range of one is >= the other <| ExplicitSimplify conditions on instructions which only care about sign on possibly NaN/Inf values <| ExplicitSimplify cmp sequences on possibly NaN/Inf values <| ExplicitSimplify pow on possibly NaN/Inf values <| ExplicitSimplify integer fraction on possibly NaN/Inf values <| ExplicitCombineInstructions can create dots <| Explicitvectorize tunnel through mul <| Explicitvectorize tunnel through neg <| Explicitvectorize tunnel through add <| ExplicitChange swizzle of parameters to dot <| Explicitnegate modifier match <| Explicitsat instruction to sat modifier match <| Explicitabs instruction to abs modifier match <| Explicitinteger negate modifier match <| Explicitmax of neg idenity to abs instruction match <| ExplicitDon't use marker values for clamped literal conversions <| Explicitpropogate swizzles <| Explicitattempt to group scalar values read by similar instructions <| ExplicitEmit return instructions <| ExplicitEmit output arrays <| ExplicitTunnel through temp arrays on load <| ExplicitInitialize arrays to void <| ExplicitConservative correctness checking <| ExplicitBasic correctness checking <| Explicitemit write masks on sample instructions <| Explicitreorder instructions to minimize register load <| ExplicitUse replicate swizzles to squish literal arrays <| ExplicitTry swizzling literal arrays to fit them together <| ExplicitTry to match temp array loads to their original store <| ExplicitRemove temp array stores that are immediately overwritten <| ExplicitDo not reduce literals in no-opt compiles <| ExplicitTry to reduce known values to movs <| ExplicitTry to combine like instructions <| ExplicitRemove args for CBuffers that are never read <| ExplicitHoist predicated code into outermost predicate <| Explicitsearch for instancing opportunities in hull shaders <| Explicitenable instancing searches for programs with multiple outputs <| Explicitsimplify flow control that writes the same value in each flow control path <| ExplicitDo not remove unaliasable array loads in no-opt compiles <| ExplicitDo not reduce switches in no-opt compiles <| Explicitcombine simple instructions to reduce instruction count <| ExplicitCompact Registers - Paint  <| ExplicitCompact Registers - Press Moves <| ExplicitCompact Registers - Press Loop Ins <| ExplicitCompact Registers - Compress <| Explicitmov of sampler register reduction <| Explicitdetect errors induced by race conditions <| Explicitif(x){} else {...} -> if(!x) {...} <| Explicitif(x){...} else {} -> if(x) {...} <| Explicitif(x){...} if(x){...} -> if(x) {... ...} <| Explicituse flow control and logical conditions to tighten ranges <| Explicitif(A){B = A ? C : D} -> if(A){B = C} <| ExplicitA = B ? B : C -> A = B ? TRUE : C} <| ExplicitA = B || !B -> A = B || TRUE <| Explicitmovc(c,ignore,a) -> mov(a) <| MR.GenSimplifyInstructionsAlways_Bothmovc(c,a,ignore) -> mov(a) <| MR.GenSimplifyInstructionsAlways_Bothmovc(c,ignore,ignore) -> ignore(0) <| MR.GenSimplifyInstructionsAlways_Bothdmovc(c,ignore,a) -> dmov(a) <| MR.GenSimplifyInstructionsAlways_Bothdmovc(c,a,ignore) -> dmov(a) <| MR.GenSimplifyInstructionsAlways_Bothdmovc(c,ignore,ignore) -> ignore(0) <| MR.GenSimplifyInstructionsAlways_Bothbreak never match (to NOP) <| MR.GenSimplifyInstructionsAlways_Bothcontinue never match (to NOP) <| MR.GenSimplifyInstructionsAlways_Bothreturn never match (to NOP) <| MR.GenSimplifyInstructionsAlways_BothNOT BLT => BGE <| MR.GenSimplifyInstructionsOpt1_ExclNOT BGE => BLT <| MR.GenSimplifyInstructionsOpt1_ExclNOT BLT => BGE (safe) <| MR.GenSimplifyInstructionsOpt1_ExclNOT BGE => BLT (safe) <| MR.GenSimplifyInstructionsOpt1_ExclNOT BEQ => BNE <| MR.GenSimplifyInstructionsOpt1_ExclNOT BNE => BEQ <| MR.GenSimplifyInstructionsOpt1_ExclNOT BILT => BIGE <| MR.GenSimplifyInstructionsOpt1_ExclNOT BIGE => BILT <| MR.GenSimplifyInstructionsOpt1_ExclNOT BIEQ => BINE <| MR.GenSimplifyInstructionsOpt1_ExclNOT BINE => BIEQ <| MR.GenSimplifyInstructionsOpt1_ExclNOT BULT => BUGE <| MR.GenSimplifyInstructionsOpt1_ExclNOT BUGE => BULT <| MR.GenSimplifyInstructionsOpt1_Excla*(1/(b*a)) -> 1 / b <| MR.GenSimplifyInstructionsOpt1_Exclrsq(x) * rsq(x) -> rcp(x) <| MR.GenSimplifyInstructionsOpt1_Exclrsq(x) * rsq(x) -> rcp(x) for positive x <| MR.GenSimplifyInstructionsOpt1_Exclcombine AND of two equal unknown left shifts <| MR.GenSimplifyInstructionsOpt1_Exclcombine AND of two equal unknown right shifts <| MR.GenSimplifyInstructionsOpt1_Exclcombine AND of two equal unknown unsigned right shifts <| MR.GenSimplifyInstructionsOpt1_Exclback-propagate negate through iadd <| MR.GenSimplifyInstructionsOpt1_Exclback-propagate negate through imul <| MR.GenSimplifyInstructionsOpt1_Exclishl(ishl(a, b), c) : if( nooverflow_mod_32(b, c) ) -> ishl(a, iadd(b, c)) <| MR.GenSimplifyInstructionsOpt1_Exclushr(ishl(a, bv), cv) : if( ge_mod_32(cv, bv) ) -> and(ushr(a, cv - bv), (1 << (32-cv))-1) <| MR.GenSimplifyInstructionsOpt1_Exclishr(ishr(a, b), c) : if( nooverflow_mod_32(b, c) ) -> ishr(a, iadd(b, c)) <| MR.GenSimplifyInstructionsOpt1_Excl(a & b) | (a & c) -> and(a, b | c) <| MR.GenSimplifyInstructionsOpt1_Exclb | (a & c) | (a & d) -> or(b, and(a, or(c,d)) <| MR.GenSimplifyInstructionsOpt1_Excland(or(a, iv1), iv2) -> or(and(a, iv2), and(iv1, iv2)) <| MR.GenSimplifyInstructionsOpt1_Exclor(and(a, iv1), iv2) if(and_ne_zero(iv1, iv2) -> or(and(a, iv1 & ~iv2), iv2) <| MR.GenSimplifyInstructionsOpt1_Exclu/ishr/l(or(a, iv1), iv2) -> or(u/ishr/l(a, iv2), u/ishr/l(iv1, iv2)) <| MR.GenSimplifyInstructionsOpt1_Exclu/ishr/l(and(a, iv1), iv2) -> and(u/ishr/l(a, iv2), u/ishr/l(iv1, iv2)) <| MR.GenSimplifyInstructionsOpt1_Exclu/ishr/l(xor(a, iv1), iv2) -> xor(u/ishr/l(a, iv2), u/ishr/l(iv1, iv2)) <| MR.GenSimplifyInstructionsOpt1_Exclishl(imul(a, iv1), iv2) : if(low_bit_clear(iv2)) -> imul(ishl(a, iv2/2), ishl(iv1, iv2/2)) <| MR.GenSimplifyInstructionsOpt1_Exclishl(ineg(a), iv1) -> ineg(ishl(a, iv1)) <| MR.GenSimplifyInstructionsOpt1_Exclishl(iadd(a, iv1), iv2) -> iadd(ishl(a, iv2), ishl(iv1, iv2)) <| MR.GenSimplifyInstructionsOpt1_Exclimul(iadd(a, iv1), iv2) -> iadd(imul(a, iv2), imul(iv1, iv2)) <| MR.GenSimplifyInstructionsOpt1_Exclushr(ushr(a, b), c) : if( nooverflow_mod_32(b, c) ) -> ushr(a, iadd(b, c)) <| MR.GenSimplifyInstructionsOpt1_Exclsplit literal sum ishl to allow literalization <| MR.GenSimplifyInstructionsOpt1_Exclsplit literal sum ishr to allow literalization <| MR.GenSimplifyInstructionsOpt1_Exclsplit literal sum ushr to allow literalization <| MR.GenSimplifyInstructionsOpt1_Excla = bfi(w, o, v, 0i) | r : if( mask_is_zero(w,o,r) ) -> bfi(w, o, v, r) <| MR.GenSimplifyInstructionsOpt1_Exclr | (a = bfi(w, o, v, 0i)) : if( mask_is_zero(w,o,r) ) -> bfi(w, o, v, r) <| MR.GenSimplifyInstructionsOpt1_Exclbfi(w, o, v, n) << s -> bfi(w, o+s, v, n) <| MR.GenSimplifyInstructionsOpt1_Exclubfe(w, o, a) >> s -> ubfe(w, o + s, a) <| MR.GenSimplifyInstructionsOpt1_Exclubfe(w, o, (a >> s) & m) : if( o + s < 32 ) -> ubfe(w, o + s, a & (m << s)) <| MR.GenSimplifyInstructionsOpt1_Exclibfe(w, o, (a >> s) & m) : if( o + s < 32 ) -> ibfe(w, o + s, a & (m << s)) <| MR.GenSimplifyInstructionsOpt1_Exclibfe(w, o, ((uint)a >> s) & m) : if( w + o + s < 32 ) -> ibfe(w, o + s, a & (m << s)) <| MR.GenSimplifyInstructionsOpt1_Excl-sin(x) -> sin(-x) <| MR.GenSimplifyInstructionsOpt1_Excl-dtof(x) -> dtof(-x) <| MR.GenSimplifyInstructionsOpt1_Excl-ftod(x) -> ftod(-x) <| MR.GenSimplifyInstructionsOpt1_Exclbfi(w, 0i, n, n) -> mov(n) <| MR.GenSimplifyInstructionsOpt1_NoExclbfi(w, o, v, bfi(w, o, 0, n)) -> bfi(w, o, v, n) <| MR.GenSimplifyInstructionsOpt1_NoExclbfi(w, o, v, n) << s -> bfi(w, o+s, v, n) <| MR.GenSimplifyInstructionsOpt1_NoExclbfi(w, 0, v, n << w) : if( w != 0 ) -> bfi(32-w, w, n, v) <| MR.GenSimplifyInstructionsOpt1_NoExcl(bfi(w, o, 0, n) | bfi(w, o, v, 0)) -> bfi(w, o, v, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(bfi(w, 0i, 0, n) | ubfe(w, 0i, v)) -> bfi(w, 0i, v, n) <| MR.GenSimplifyInstructionsOpt1_NoExclubfe(w, 0i, a) << o -> bfi(w, o, a, 0i) <| MR.GenSimplifyInstructionsOpt1_NoExclbfi(w, 0i, a, 0i) -> ubfe(w, 0i, a) <| MR.GenSimplifyInstructionsOpt1_NoExclubfe(w, 0i, a >> s) -> ubfe(w, s, a) <| MR.GenSimplifyInstructionsOpt1_NoExclubfe(w, o, a >> s) : if( o + s < 32 ) -> ubfe(w, o + s, a) <| MR.GenSimplifyInstructionsOpt1_NoExclibfe(w, o, a >> s) : if( o + s < 32 ) -> ibfe(w, o + s, a) <| MR.GenSimplifyInstructionsOpt1_NoExclibfe(w, o, (uint)a >> s) : if( o + s + w < 32 ) -> ibfe(w, o + s, a) <| MR.GenSimplifyInstructionsOpt1_NoExclubfe(w, o, a) >> s : if( o + s < 32 && w >= s ) -> ubfe(w - s, o + s, a) <| MR.GenSimplifyInstructionsOpt1_NoExclibfe(w, o, a) >> s : if( o + s < 32 && w >= s ) -> ibfe(w - s, o + s, a) <| MR.GenSimplifyInstructionsOpt1_NoExclb = ubfe(w, o, a); movc(b & (1 << (w - 1 + o)), b | ~((1 << w + o)-1), b) -> ibfe(w, o, a) <| MR.GenSimplifyInstructionsOpt1_NoExcla = bfi(w, o, v, 0i) | r : if( mask_is_zero(w,o,r) ) -> bfi(w, o, v, r) <| MR.GenSimplifyInstructionsOpt1_NoExcla = bfi(w, o, v, and(m, r)) : if( unmasked_is_one_or_val_is_zero(w,o,v,m) ) -> bfi(w, o, v, r) <| MR.GenSimplifyInstructionsOpt1_NoExcla = bfi(w, o, v, and(r, m)) : if( unmasked_is_one_or_val_is_zero(w,o,v,m) ) -> bfi(w, o, v, r) <| MR.GenSimplifyInstructionsOpt1_NoExcla = bfi(w, o, and(v, m), r) : if( masked_is_one(w,o,m) ) -> bfi(w, o, v, r) <| MR.GenSimplifyInstructionsOpt1_NoExcla = bfi(w, o, and(m, v), r) : if( masked_is_one(w,o,m) ) -> bfi(w, o, v, r) <| MR.GenSimplifyInstructionsOpt1_NoExclbfi(and(w,31), o, v, r) : if( lower_5_bits_are_set(31) ) -> bfi(w, o, v, r) <| MR.GenSimplifyInstructionsOpt1_NoExclbfi(and(31,w), o, v, r) : if( lower_5_bits_are_set(31) ) -> bfi(w, o, v, r) <| MR.GenSimplifyInstructionsOpt1_NoExclbfi(w, and(o,31), v, r) : if( lower_5_bits_are_set(31) ) -> bfi(w, o, v, r) <| MR.GenSimplifyInstructionsOpt1_NoExclbfi(w, and(31,o), v, r) : if( lower_5_bits_are_set(31) ) -> bfi(w, o, v, r) <| MR.GenSimplifyInstructionsOpt1_NoExclabs(a), a positive -> a <| MR.GenSimplifyInstructionsOpt1_NoExclabs(a), a negative -> neg(a) <| MR.GenSimplifyInstructionsOpt1_NoExclbine for isfinite on finite -> true <| MR.GenSimplifyInstructionsOpt1_NoExclfrc(a + int) = frc(a) <| MR.GenSimplifyInstructionsOpt1_NoExcl$IsRound(fp int) = mov(fp int) <| MR.GenSimplifyInstructionsOpt1_NoExcladd of zero identity <| MR.GenSimplifyInstructionsOpt1_NoExcldouble add of zero identity <| MR.GenSimplifyInstructionsOpt1_NoExcladd of negative of itself identity <| MR.GenSimplifyInstructionsOpt1_NoExclLegacy (!A + A) => 1 + B <| MR.GenSimplifyInstructionsOpt1_NoExclLegacy !A + (A + B) => 1 + B <| MR.GenSimplifyInstructionsOpt1_NoExclLegacy C + (A * B) + (A * !B) => C + A <| MR.GenSimplifyInstructionsOpt1_NoExclLERP(!A,B,C) -> LERP(A, C, B) <| MR.GenSimplifyInstructionsOpt1_NoExcleval eq <| MR.GenSimplifyInstructionsOpt1_NoExcleval bne on non-nan value <| MR.GenSimplifyInstructionsOpt1_NoExcleval ge <| MR.GenSimplifyInstructionsOpt1_NoExclbinary expression with negative symmetry reduction <| MR.GenSimplifyInstructionsOpt1_NoExclbge(mul(x,x),neg(mul(x,x))) -> true <| MR.GenSimplifyInstructionsOpt1_NoExclIGE a,a -> true <| MR.GenSimplifyInstructionsOpt1_NoExclILT a,a -> false <| MR.GenSimplifyInstructionsOpt1_NoExclbine(ishl(a, n),0) : if(upper_n_bits_are_zero(a, n)) -> bine (a, 0) <| MR.GenSimplifyInstructionsOpt1_NoExclbine(i/ushr(a, n),0) : if(lower_n_bits_are_zero(a, n)) -> bine (a, 0) <| MR.GenSimplifyInstructionsOpt1_NoExcldtoi(itod(x)) -> mov(x) <| MR.GenSimplifyInstructionsOpt1_NoExcldtou(utod(x)) -> mov(x) <| MR.GenSimplifyInstructionsOpt1_NoExcltrunc(utod(x)) -> utod(x) <| MR.GenSimplifyInstructionsOpt1_NoExcldtof(ftod(x)) -> mov(x) <| MR.GenSimplifyInstructionsOpt1_NoExcl(a != b) ? a : b -> a <| MR.GenSimplifyInstructionsOpt1_NoExcl(a != b) ? b : a -> b <| MR.GenSimplifyInstructionsOpt1_NoExcl(a == b) ? a : b -> b <| MR.GenSimplifyInstructionsOpt1_NoExcl(a == b) ? b : a -> a <| MR.GenSimplifyInstructionsOpt1_NoExcl(a == (b ? c : a)) : if (c != a) -> b == 0 <| MR.GenSimplifyInstructionsOpt1_NoExcl(a == (b ? a : c)) : if (c != a) -> b != 0 <| MR.GenSimplifyInstructionsOpt1_NoExclfirstbit*(x) != -1 -> x != 0 <| MR.GenSimplifyInstructionsOpt1_NoExclfirstbit*(x) == -1 -> x == 0 <| MR.GenSimplifyInstructionsOpt1_NoExclx ? firstbit*(x) : -1 -> firstbit*(x) <| MR.GenSimplifyInstructionsOpt1_NoExcl$IsAnyShift(x, and(y, 31)) <| MR.GenSimplifyInstructionsOpt1_NoExcl$IsAnyShift(x, and(31, y)) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(ishl(a, n),v1, v2) : if(upper_n_bits_are_zero(a, n)) -> movc (a, v1, v2) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(i/ushr(a, n),v1, v2) : if(lower_n_bits_are_zero(a, n)) -> movc (a, v1, v2) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(a, i/ushr/l(a, n), 0) -> i/ushr/l(a, n) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(a, b, i/ushr/l(a, n)) -> movc(a, b, 0) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(u/ishr/l(a, n), movc(a, b, c), d) -> movc(u/ishr/l(a, n), b, d) <| MR.GenSimplifyInstructionsOpt1_NoExclA+A REL L <| MR.GenSimplifyInstructionsOpt1_NoExclL REL A+A <| MR.GenSimplifyInstructionsOpt1_NoExclA*(L2>0) REL L <| MR.GenSimplifyInstructionsOpt1_NoExclL REL A*(L2>0) <| MR.GenSimplifyInstructionsOpt1_NoExclA*(L2<0) REL L <| MR.GenSimplifyInstructionsOpt1_NoExclL REL A*(L2<0) <| MR.GenSimplifyInstructionsOpt1_NoExclA+A REL L (double) <| MR.GenSimplifyInstructionsOpt1_NoExclL REL A+A (double) <| MR.GenSimplifyInstructionsOpt1_NoExclA*(L2>0) REL L (double) <| MR.GenSimplifyInstructionsOpt1_NoExclL REL A*(L2>0) (double) <| MR.GenSimplifyInstructionsOpt1_NoExclA*(L2<0) REL L (double) <| MR.GenSimplifyInstructionsOpt1_NoExclL REL A*(L2<0) (double) <| MR.GenSimplifyInstructionsOpt1_NoExclA*L2 REL L where L2 divides L as a UINT <| MR.GenSimplifyInstructionsOpt1_NoExclL REL A*L2 where L2 divides L as a UINT <| MR.GenSimplifyInstructionsOpt1_NoExclA*L2 REL L where L2 > 0 divides L as an INT <| MR.GenSimplifyInstructionsOpt1_NoExclL REL A*L2 where L2 > 0 divides L as an INT <| MR.GenSimplifyInstructionsOpt1_NoExclA*L2 REL L where L2 < 0 divides L as an INT <| MR.GenSimplifyInstructionsOpt1_NoExclL REL A*L2 where L2 < 0 divides L as an INT <| MR.GenSimplifyInstructionsOpt1_NoExcleval lt <| MR.GenSimplifyInstructionsOpt1_NoExclbtof -> movc <| MR.GenSimplifyInstructionsOpt1_NoExclbtoi -> movc <| MR.GenSimplifyInstructionsOpt1_NoExclUGE a,a -> true <| MR.GenSimplifyInstructionsOpt1_NoExclULT a,a -> false <| MR.GenSimplifyInstructionsOpt1_NoExclsimplify chain merges that bring in chain input <| MR.GenSimplifyInstructionsOpt1_NoExclsimplify chain merges that bring in chain input via mov right <| MR.GenSimplifyInstructionsOpt1_NoExclsimplify chain merges that bring in chain input via mov left <| MR.GenSimplifyInstructionsOpt1_NoExclsimplify chain merges that repeatedly chain in the same value <| MR.GenSimplifyInstructionsOpt1_NoExclsimplify array merges that repeatedly chain in the same value <| MR.GenSimplifyInstructionsOpt1_NoExclclip(a+a,b) -> clip(a,b) <| MR.GenSimplifyInstructionsOpt1_NoExclclip(+d * a,b) -> clip(a,b) <| MR.GenSimplifyInstructionsOpt1_NoExclnullify clip ops on known positive values <| MR.GenSimplifyInstructionsOpt1_NoExclremove clips that are merged with known-success clips <| MR.GenSimplifyInstructionsOpt1_NoExclremove clip chains that are merged with known-success clips <| MR.GenSimplifyInstructionsOpt1_NoExclcmp(+d * a,b,c) -> cmp(a,b,c) <| MR.GenSimplifyInstructionsOpt1_NoExclcmp(-d * a,b,c) -> cmp(-a,b,c) <| MR.GenSimplifyInstructionsOpt1_NoExclcmp(-b,0,b) -> cmp(b,b,0) <| MR.GenSimplifyInstructionsOpt1_NoExclcmp of known positive identity <| MR.GenSimplifyInstructionsOpt1_NoExclcmp of known negative identity <| MR.GenSimplifyInstructionsOpt1_NoExclcmp(a+a,b,c) -> cmp(a,b,c) <| MR.GenSimplifyInstructionsOpt1_NoExclsymmetric cmp <| MR.GenSimplifyInstructionsOpt1_NoExclcmp(cmp(a, >=0, <0), b, c) -> cmp(a,b,c) <| MR.GenSimplifyInstructionsOpt1_NoExclcmp(cmp(a, <0, >=0), b, c) -> cmp(a,c,b) <| MR.GenSimplifyInstructionsOpt1_NoExclcmp(-cmp(a, <=0, >0), b, c) -> cmp(a,b,c) <| MR.GenSimplifyInstructionsOpt1_NoExclcmp(-cmp(a, >0, <=0), b, c) -> cmp(a,c,b) <| MR.GenSimplifyInstructionsOpt1_NoExclLegacy NOT (A || A) => NOT A <| MR.GenSimplifyInstructionsOpt1_NoExclCMP(c,d=1+CMP(c,a,b),f) -> CMP(c,1+a,f) <| MR.GenSimplifyInstructionsOpt1_NoExclnullify discard ops on known false values <| MR.GenSimplifyInstructionsOpt1_NoExclremove discards that are merged with known-success discards <| MR.GenSimplifyInstructionsOpt1_NoExclremove discard chains that are merged with known-success discards <| MR.GenSimplifyInstructionsOpt1_NoExclmerge discard_nz test with an earlier bine comparison <| MR.GenSimplifyInstructionsOpt1_NoExclmerge discard_z test with an earlier bine comparison <| MR.GenSimplifyInstructionsOpt1_NoExclmerge and flip discard_nz test with an earlier bieq comparison <| MR.GenSimplifyInstructionsOpt1_NoExclmerge and flip discard_z test with an earlier bieq comparison <| MR.GenSimplifyInstructionsOpt1_NoExcldivision by a literal becomes multiplication by reciprocal <| MR.GenSimplifyInstructionsOpt1_NoExcl1 / x -> rcp(x) <| MR.GenSimplifyInstructionsOpt1_NoExclx / x -> 1 <| MR.GenSimplifyInstructionsOpt1_NoExcldot(normalized_v, normalized_v) == 1.0 when v has length <| MR.GenSimplifyInstructionsOpt1_NoExclexp(log(x)) identity <| MR.GenSimplifyInstructionsOpt1_NoExclftob(trunc(btof(x))) -> mov(x) <| MR.GenSimplifyInstructionsOpt1_NoExclftoi(itof(x)) -> mov(x) <| MR.GenSimplifyInstructionsOpt1_NoExcltrunc(itof(x)) -> itof(x) <| MR.GenSimplifyInstructionsOpt1_NoExclftou(utof(x)) -> mov(x) <| MR.GenSimplifyInstructionsOpt1_NoExcltrunc(utof(x)) -> utof(x) <| MR.GenSimplifyInstructionsOpt1_NoExclLegacy NOT GE => LT <| MR.GenSimplifyInstructionsOpt1_NoExclLegacy NOT LT => GE <| MR.GenSimplifyInstructionsOpt1_NoExcliadd zero reduces to no-op mov <| MR.GenSimplifyInstructionsOpt1_NoExclInteger addition negative identities <| MR.GenSimplifyInstructionsOpt1_NoExcliadd(a, b) : if( and_is_zero(a, b) ) -> or(a, b) <| MR.GenSimplifyInstructionsOpt1_NoExclif(bine(x,0)) -> if(x) <| MR.GenSimplifyInstructionsOpt1_NoExclimul one reduces to no-op mov <| MR.GenSimplifyInstructionsOpt1_NoExclineg(and(ne(x,0),1)) -> ne(x,0) <| MR.GenSimplifyInstructionsOpt1_NoExclineg(ineg(x)) -> mov(x) <| MR.GenSimplifyInstructionsOpt1_NoExclu/ishl/r(a, 0) -> mov(a) <| MR.GenSimplifyInstructionsOpt1_NoExcl((a >> ov1) << o2) : if( ov1 == o2 ) -> and(a, ~((1 << ov1)-1)) <| MR.GenSimplifyInstructionsOpt1_NoExclu/ishr(or(a, m), n) : if( or_is_identity_ignore_lower_n_bits(a, m, n) -> u/ishr(a, n) <| MR.GenSimplifyInstructionsOpt1_NoExclu/ishr(or(m, a), n) : if( or_is_identity_ignore_lower_n_bits(a, m, n) -> u/ishr(a, n) <| MR.GenSimplifyInstructionsOpt1_NoExclu/ishr(and(a, m), n) : if( and_is_identity_ignore_lower_n_bits(a, m, n) -> u/ishr(a, n) <| MR.GenSimplifyInstructionsOpt1_NoExclu/ishr(and(m, a), n) : if( and_is_identity_ignore_lower_n_bits(a, m, n) -> u/ishr(a, n) <| MR.GenSimplifyInstructionsOpt1_NoExclishl(or(a, m), n) : if( or_is_identity_ignore_upper_n_bits(a, m, n) -> ishl(a, n) <| MR.GenSimplifyInstructionsOpt1_NoExclishl(or(m, a), n) : if( or_is_identity_ignore_upper_n_bits(a, m, n) -> ishl(a, n) <| MR.GenSimplifyInstructionsOpt1_NoExclishl(and(a, m), n) : if( and_is_identity_ignore_upper_n_bits(a, m, n) -> ishl(a, n) <| MR.GenSimplifyInstructionsOpt1_NoExclishl(and(m, a), n) : if( and_is_identity_ignore_upper_n_bits(a, m, n) -> ishl(a, n) <| MR.GenSimplifyInstructionsOpt1_NoExclimul(ishl(iv1, a), iv2) -> ishl(imul(iv1, iv2), a) <| MR.GenSimplifyInstructionsOpt1_NoExclA + B for boolean A & B -> OR A, B <| MR.GenSimplifyInstructionsOpt1_NoExclA * B for boolean A & B -> AND A, B <| MR.GenSimplifyInstructionsOpt1_NoExclitob(x) -> bine(x,0) <| MR.GenSimplifyInstructionsOpt1_NoExclitof(ftoi(x)) -> trunc(x) <| MR.GenSimplifyInstructionsOpt1_NoExcllog(exp(x)) identity <| MR.GenSimplifyInstructionsOpt1_NoExclexp(a*log(0)) = 0 identity <| MR.GenSimplifyInstructionsOpt1_NoExclLegacy -BOOL < BOOL => BOOL <| MR.GenSimplifyInstructionsOpt1_NoExclLegacy (A || A) => A <| MR.GenSimplifyInstructionsOpt1_NoExclmax(i0, i1): if (i0 >= i1) -> mov(i0) <| MR.GenSimplifyInstructionsOpt1_NoExclmax(i0, i1): if (i1 >= i0) -> mov(i1) <| MR.GenSimplifyInstructionsOpt1_NoExclmax(max(i0, l1), l2) -> max(i0, max(l1, l2)) <| MR.GenSimplifyInstructionsOpt1_NoExcldmax(i0, i1): if (i0 >= i1) -> mov(i0) <| MR.GenSimplifyInstructionsOpt1_NoExcldmax(i0, i1): if (i1 >= i0) -> mov(i1) <| MR.GenSimplifyInstructionsOpt1_NoExcldmax(dmax(i0, l1), l2) -> dmax(i0, dmax(l1, l2)) <| MR.GenSimplifyInstructionsOpt1_NoExclimax(i0, i1): if (i0 >= i1) -> mov(i0) <| MR.GenSimplifyInstructionsOpt1_NoExclimax(i0, i1): if (i1 >= i0) -> mov(i1) <| MR.GenSimplifyInstructionsOpt1_NoExclimax(imax(i0, l1), l2) -> imax(i0, imax(l1, l2)) <| MR.GenSimplifyInstructionsOpt1_NoExclumax(i0, i1): if (i0 >= i1) -> mov(i0) <| MR.GenSimplifyInstructionsOpt1_NoExclumax(i0, i1): if (i1 >= i0) -> mov(i1) <| MR.GenSimplifyInstructionsOpt1_NoExclumax(umax(i0, l1), l2) -> umax(i0, umax(l1, l2)) <| MR.GenSimplifyInstructionsOpt1_NoExclmin(i0, i1): if (i0 >= i1) -> mov(i1) <| MR.GenSimplifyInstructionsOpt1_NoExclmin(i0, i1): if (i1 >= i0) -> mov(i0) <| MR.GenSimplifyInstructionsOpt1_NoExclmin(min(i0, l1), l2) -> min(i0, min(l1, l2)) <| MR.GenSimplifyInstructionsOpt1_NoExcldmin(i0, i1): if (i0 >= i1) -> mov(i1) <| MR.GenSimplifyInstructionsOpt1_NoExcldmin(i0, i1): if (i1 >= i0) -> mov(i0) <| MR.GenSimplifyInstructionsOpt1_NoExcldmin(dmin(i0, l1), l2) -> dmin(i0, dmin(l1, l2)) <| MR.GenSimplifyInstructionsOpt1_NoExclimin(i0, i1): if (i0 >= i1) -> mov(i1) <| MR.GenSimplifyInstructionsOpt1_NoExclimin(i0, i1): if (i1 >= i0) -> mov(i0) <| MR.GenSimplifyInstructionsOpt1_NoExclimin(imin(i0, l1), l2) -> imin(i0, imin(l1, l2)) <| MR.GenSimplifyInstructionsOpt1_NoExclumin(i0, i1): if (i0 >= i1) -> mov(i1) <| MR.GenSimplifyInstructionsOpt1_NoExclumin(i0, i1): if (i1 >= i0) -> mov(i0) <| MR.GenSimplifyInstructionsOpt1_NoExclumin(umin(i0, l1), l2) -> umin(i0, umin(l1, l2)) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(a,true,false) -> bine(a, 0) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(a,false,true) -> bieq(a, 0) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(true,b,c) -> mov(b) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(false,b,c) -> mov(c) <| MR.GenSimplifyInstructionsOpt1_NoExcldmovc(true,b,c) -> dmov(b) <| MR.GenSimplifyInstructionsOpt1_NoExcldmovc(false,b,c) -> dmov(c) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(a, true, b) -> or(a, b) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc and comparison sequence reductions <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(a, b, movc(c, b, d)) -> movc(or(a, c), b, d) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(a, b, and(c, b)) -> and(or(a, c), b) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(a, and(b, c), 0) -> and(and(a, b), c) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(!a,b,c) -> movc(a,c,b) <| MR.GenSimplifyInstructionsOpt1_NoExcldmovc(!a,b,c) -> dmovc(a,c,b) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(movc(a,TRUE,FALSE),b,c) -> movc(a,b,c) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(movc(a,FALSE,TRUE),b,c) -> movc(a,c,b) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(bool b, TRUE, FALSE) -> mov b <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(bool b, FALSE, TRUE) -> not b <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(bool b, TRUE, bool c) -> or(b,c) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(bool b, bool b, false) -> mov b <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(b, a, b) -> movc (b, a, 0) <| MR.GenSimplifyInstructionsOpt1_NoExcl(n > i) ? X : umin(n, i) -> (i > n) ? X: i <| MR.GenSimplifyInstructionsOpt1_NoExclbool ? a + 1 : a -> a - bool <| MR.GenSimplifyInstructionsOpt1_NoExclbool ? a - 1 : a -> a + bool <| MR.GenSimplifyInstructionsOpt1_NoExcl(n > i) ? X : imin(n, i) -> (i > n) ? X: i <| MR.GenSimplifyInstructionsOpt1_NoExcl(n > i) ? X : min(n, i) -> (i > n) ? X: i <| MR.GenSimplifyInstructionsOpt1_NoExcl(n > i) ? X : dmin(n, i) -> (i > n) ? X: i <| MR.GenSimplifyInstructionsOpt1_NoExcl(V < n) ? V : n -> min(V, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(V < n) ? (V+1) : n -> min(V+1, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(n >= V) ? V : n -> min(V, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(V < n) ? V : n -> dmin(V, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(V < n) ? (V+1) : n -> dmin(V+1, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(n >= V) ? V : n -> dmin(V, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(0 < n) ? 1 : 0 -> umin(1, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(V < n) ? V : n -> umin(V, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(V < n) ? (V+1) : n -> umin(V+1, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(n >= V) ? V : n -> umin(V, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(V < n) ? V : n -> imin(V, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(V < n) ? (V+1) : n -> imin(V+1, n) <| MR.GenSimplifyInstructionsOpt1_NoExcl(n >= V) ? V : n -> imin(V, n) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(a,b,b) -> mov(b) <| MR.GenSimplifyInstructionsOpt1_NoExcldmovc(a,b,b) -> dmov(b) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc((a max(a,b) <| MR.GenSimplifyInstructionsOpt1_NoExclinteger movc((a max(a,b) <| MR.GenSimplifyInstructionsOpt1_NoExclunsigned integer movc((a max(a,b) <| MR.GenSimplifyInstructionsOpt1_NoExcldmovc((a dmax(a,b) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc((a>=b),a,b) -> max(a,b) <| MR.GenSimplifyInstructionsOpt1_NoExclinteger movc((a>=b),a,b) -> max(a,b) <| MR.GenSimplifyInstructionsOpt1_NoExclunsigned integer movc((a>=b),a,b) -> max(a,b) <| MR.GenSimplifyInstructionsOpt1_NoExcldmovc((a>=b),a,b) -> dmax(a,b) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(c,d=movc(c,a,b),f) -> movc(c,a,f) <| MR.GenSimplifyInstructionsOpt1_NoExclmovc(c,f,d=movc(c,a,b)) -> movc(c,f,b) <| MR.GenSimplifyInstructionsOpt1_NoExclcmp(c,d=cmp(c,a,b),f) -> cmp(c,a,f) <| MR.GenSimplifyInstructionsOpt1_NoExclcmp(c,f,d=cmp(c,a,b)) -> cmp(c,f,b) <| MR.GenSimplifyInstructionsOpt1_NoExclmul of one identity <| MR.GenSimplifyInstructionsOpt1_NoExclmul of double one identity <| MR.GenSimplifyInstructionsOpt1_NoExcl(A + A) * 0.5 -> no-op mov of A <| MR.GenSimplifyInstructionsOpt1_NoExclmul of a number times its inverse identity <| MR.GenSimplifyInstructionsOpt1_NoExclA * B/A with negative variations on A <| MR.GenSimplifyInstructionsOpt1_NoExclnormalize(normalize(v)) -> normalize(v) <| MR.GenSimplifyInstructionsOpt1_NoExclLegacy !A * (A + B) => !A * B <| MR.GenSimplifyInstructionsOpt1_NoExclLegacy A * !(A * B) => A * !B <| MR.GenSimplifyInstructionsOpt1_NoExclLegacy (!A * A) => 0 <| MR.GenSimplifyInstructionsOpt1_NoExclB*!(A * -B + B) -> A * B <| MR.GenSimplifyInstructionsOpt1_NoExcldouble negative to original <| MR.GenSimplifyInstructionsOpt1_NoExclor(ine(x,0),ine(y,0)) -> ine(or(x,y),0) <| MR.GenSimplifyInstructionsOpt1_NoExclcombine OR of two equal shifts <| MR.GenSimplifyInstructionsOpt1_NoExclcombine XOR of two equal shifts <| MR.GenSimplifyInstructionsOpt1_NoExclX AND ~X => 0 <| MR.GenSimplifyInstructionsOpt1_NoExclX AND Y : if( and_is_identity(x,y) => X <| MR.GenSimplifyInstructionsOpt1_NoExclX AND Y : if( and_is_identity(y,x) => Y <| MR.GenSimplifyInstructionsOpt1_NoExcland(and(a, b), c) : if( and_is_identity(c, b) ) -> and(a, c) <| MR.GenSimplifyInstructionsOpt1_NoExcland(and(b, a), c) : if( and_is_identity(c, b) ) -> and(a, c) <| MR.GenSimplifyInstructionsOpt1_NoExcland(a, iv2) : if( can_reduce_and(a, iv2) ) -> and(a, get_reduced_and(a, iv2)) <| MR.GenSimplifyInstructionsOpt1_NoExclX OR ~X => btrue <| MR.GenSimplifyInstructionsOpt1_NoExclX OR Y : if( or_is_identity(x,y) => X <| MR.GenSimplifyInstructionsOpt1_NoExclX OR Y : if( or_is_identity(y,x) => Y <| MR.GenSimplifyInstructionsOpt1_NoExclor(a, iv2) : if( can_reduce_or(a, iv2) ) -> or(a, get_reduced_or(a, iv2)) <| MR.GenSimplifyInstructionsOpt1_NoExclor(or(a, b), c) : if( or_is_identity(c, b) ) -> or(a, c) <| MR.GenSimplifyInstructionsOpt1_NoExclor(or(b, a), c) : if( or_is_identity(c, b) ) -> or(a, c) <| MR.GenSimplifyInstructionsOpt1_NoExcl(A & B) | (A & C) => (A & (B | C)) <| MR.GenSimplifyInstructionsOpt1_NoExcl(B & A) | (A & C) => (A & (B | C)) <| MR.GenSimplifyInstructionsOpt1_NoExcldouble rcp identity <| MR.GenSimplifyInstructionsOpt1_NoExcldouble drcp identity <| MR.GenSimplifyInstructionsOpt1_NoExclrcp(mul(x, rsq(x)) = rsq(x) identity <| MR.GenSimplifyInstructionsOpt1_NoExcl1 / sqrt(x) -> rsq(x) <| MR.GenSimplifyInstructionsOpt1_NoExclsqrt times sqrt of positive value equals the original value identity <| MR.GenSimplifyInstructionsOpt1_NoExclpositive sqrt(x*x) identity <| MR.GenSimplifyInstructionsOpt1_NoExclconvert mod by power-of-2 to bitwise AND <| MR.GenSimplifyInstructionsOpt1_NoExclutof(sampleinfo_uint(x)) -> sampleinfo(x) <| MR.GenSimplifyInstructionsOpt1_NoExclxor(xor(a, iv1), iv2) -> xor(a, xor(iv1, iv2)) <| MR.GenSimplifyInstructionsOpt1_NoExclreplace bitwise double-complement with move <| MR.GenSimplifyInstructionsOpt1_NoExclbine(b,0) -> b <| MR.GenSimplifyInstructionsOpt2_NoExclmovc(bool,x,0) -> and(bool,x) <| MR.GenSimplifyInstructionsOpt2_NoExclutof(sampleinfo_uint_rt(x)) -> sampleinfo_rt(x) <| MR.GenSimplifyInstructionsSampleMask_Bothmovc, unary_compute on values lhs -> unary_compute, movc <| MR.GenShuffleCompute_Exclmovc, unary_compute on values rhs -> unary_compute, movc <| MR.GenShuffleCompute_Exclcmp, unary_compute on values lhs -> unary_compute, cmp <| MR.GenShuffleCompute_Exclcmp, unary_compute on values rhs -> unary_compute, cmp <| MR.GenShuffleCompute_Exclmovc, binary_compute on values lhs -> binary_compute, movc <| MR.GenShuffleCompute_Exclmovc, binary_compute on values rhs -> binary_compute, movc <| MR.GenShuffleCompute_Exclcmp, binary_compute on values lhs -> binary_compute, cmp <| MR.GenShuffleCompute_Exclcmp, binary_compute on values rhs -> binary_compute, cmp <| MR.GenShuffleCompute_Exclmovc, ternary arg1 on values lhs -> ternary, movc <| MR.GenShuffleCompute_Exclmovc, ternary arg1 on values rhs -> ternary, movc <| MR.GenShuffleCompute_Exclmovc, ternary arg2 on values lhs -> ternary, movc <| MR.GenShuffleCompute_Exclmovc, ternary arg2 on values rhs -> ternary, movc <| MR.GenShuffleCompute_Exclmovc, ternary arg3 on values lhs -> ternary, movc <| MR.GenShuffleCompute_Exclmovc, ternary arg3 on values rhs -> ternary, movc <| MR.GenShuffleCompute_Exclmovc, quat arg1 on values lhs -> quat, movc <| MR.GenShuffleCompute_Exclmovc, quat arg1 on values rhs -> quat, movc <| MR.GenShuffleCompute_Exclmovc, quat arg2 on values lhs -> quat, movc <| MR.GenShuffleCompute_Exclmovc, quat arg2 on values rhs -> quat, movc <| MR.GenShuffleCompute_Exclmovc, quat arg3 on values lhs -> quat, movc <| MR.GenShuffleCompute_Exclmovc, quat arg3 on values rhs -> quat, movc <| MR.GenShuffleCompute_Exclmovc, quat arg4 on values lhs -> quat, movc <| MR.GenShuffleCompute_Exclmovc, quat arg4 on values rhs -> quat, movc <| MR.GenShuffleCompute_Exclmovc, unary_compute on values -> unary_compute, movc <| MR.GenShuffleCompute_NoExclcmp, unary_compute on values -> unary_compute, cmp <| MR.GenShuffleCompute_NoExcland, unary_compute on values -> unary_compute, and <| MR.GenShuffleCompute_NoExclmovc, binary_compute on values -> binary_compute, movc <| MR.GenShuffleCompute_NoExclmovc, binary_compute on same value -> binary_compute, movc <| MR.GenShuffleCompute_NoExclcmp, binary_compute on values -> binary_compute, cmp <| MR.GenShuffleCompute_NoExclcmp, binary_compute on same value -> binary_compute, cmp <| MR.GenShuffleCompute_NoExcland, binary_compute on values -> binary_compute, and <| MR.GenShuffleCompute_NoExclmovc, ternary arg1 on values -> ternary, movc <| MR.GenShuffleCompute_NoExclmovc, ternary arg2 on values -> ternary, movc <| MR.GenShuffleCompute_NoExclmovc, ternary arg3 on values -> ternary, movc <| MR.GenShuffleCompute_NoExcland, ternary arg1 on values -> ternary, movc <| MR.GenShuffleCompute_NoExcland, ternary arg2 on values -> ternary, movc <| MR.GenShuffleCompute_NoExcland, ternary arg3 on values -> ternary, movc <| MR.GenShuffleCompute_NoExclmovc, quat arg1 on values -> quat, movc <| MR.GenShuffleCompute_NoExclmovc, quat arg2 on values -> quat, movc <| MR.GenShuffleCompute_NoExclmovc, quat arg3 on values -> quat, movc <| MR.GenShuffleCompute_NoExclmovc, quat arg4 on values -> quat, movc <| MR.GenShuffleCompute_NoExcland, quat arg1 on values -> quat, movc <| MR.GenShuffleCompute_NoExcland, quat arg2 on values -> quat, movc <| MR.GenShuffleCompute_NoExcland, quat arg3 on values -> quat, movc <| MR.GenShuffleCompute_NoExcland, quat arg4 on values -> quat, movc <| MR.GenShuffleCompute_NoExclmad match 1 (a + b*c) <| MR.GenMadmad match 2 (a - b*c) <| MR.GenMadmad match 3 (a + b+b) <| MR.GenMadmad match 4 (a - b+b) <| MR.GenMadimad match 1 (a + b*c) <| MR.GenMadimad match 2 (a + b+b) <| MR.GenMada << L | b (bfi(w=32-L, o=L, a, b) if( mask_is_zero(w, o, b) && allbutwidth_is_zero(w, a) -> imad (a, 1 << L, B) <| MR.GenMadif+lt -> if_lt <| MR.Gen_PreModTarget_Bothif+ge -> if_ge <| MR.Gen_PreModTarget_Bothif+cmp_lt -> if_lt <| MR.Gen_PreModTarget_Bothif+cmp_ge -> if_ge <| MR.Gen_PreModTarget_Bothif+cmp_lt0 -> if_lt0 <| MR.Gen_PreModTarget_Bothif+cmp_ge0 -> if_ge0 <| MR.Gen_PreModTarget_Bothif_lt(neg(abs(x)), 0) -> if_ne0 <| MR.Gen_PreModTarget_Bothif_ge(neg(abs(x)), 0) -> if_eq0 <| MR.Gen_PreModTarget_Bothif_lt(-a^2,a^2) -> if_ne(a,0) <| MR.Gen_PreModTarget_Bothif_ge(-a^2,a^2) -> if_eq(a,0) <| MR.Gen_PreModTarget_Bothif_ne(x, 0) -> if_ne(x, -x) <| MR.Gen_PreModTarget_Bothif_ge(x + y, 0) -> if_ge(x, -y) <| MR.Gen_PreModTarget_Bothif_lt(x + y, 0) -> if_lt(x, -y) <| MR.Gen_PreModTarget_Bothif_ne(x + y, 0) -> if_ne(x, -y) <| MR.Gen_PreModTarget_Bothif_eq(x + y, 0) -> if_eq(x, -y) <| MR.Gen_PreModTarget_Bothbreak(a,not(x)) -> breakn(a,x) <| MR.Gen_PreModTarget_Bothcontinue(a,not(x)) -> continuen(a,x) <| MR.Gen_PreModTarget_Bothreturn(a,not(x)) -> returnn(a,x) <| MR.Gen_PreModTarget_Bothbreak(a,bieq(x,0)) -> breakn(a,x) <| MR.Gen_PreModTarget_Bothcontinue(a,bieq(x,0)) -> continuen(a,x) <| MR.Gen_PreModTarget_Bothreturn(a,bieq(x,0)) -> returnn(a,x) <| MR.Gen_PreModTarget_Bothbreak(a,bine(x)) -> break(a,x) <| MR.Gen_PreModTarget_Bothcontinue(a,bine(x)) -> continue(a,x) <| MR.Gen_PreModTarget_Bothreturn(a,bine(x)) -> return(a,x) <| MR.Gen_PreModTarget_Bothbreak(ge(neg(fbool), fbool)) -> break_eq(fbool, 0) <| MR.Gen_PreModTarget_BothBREAK_GE i2,i1 short form <| MR.Gen_PreModTarget_BothBREAK_GE i2,i1 for targets that use CMP <| MR.Gen_PreModTarget_BothBREAK_GE i2,-iv1 where iv1 is literal and needs to be negated before using <| MR.Gen_PreModTarget_BothBREAK_LT i2,i1 short form <| MR.Gen_PreModTarget_BothBREAK_LT i2,i1 for targets that use CMP <| MR.Gen_PreModTarget_BothBREAK_LT i2,-iv1 where iv1 is literal and needs to be negated before using <| MR.Gen_PreModTarget_BothBREAK_EQ i2,i1 <| MR.Gen_PreModTarget_BothBREAK_EQ i2,i1 matches when CMP is used <| MR.Gen_PreModTarget_BothBREAK_EQ i2,-iv1 where iv1 is literal and has to be negated <| MR.Gen_PreModTarget_BothBREAK_EQ i2,-iv1 where iv1 is literal and has to be negated, CMP form <| MR.Gen_PreModTarget_BothBREAK_NE i2,i1 <| MR.Gen_PreModTarget_BothBREAK_NE i2,i1 with CMP <| MR.Gen_PreModTarget_BothBREAK_NE i2,-iv1 where iv1 is literal and has to be negated <| MR.Gen_PreModTarget_BothBREAK_NE i2,-iv1 where iv1 is literal and has to be negated, CMP form <| MR.Gen_PreModTarget_Bothmovc(blt(a, 0), |a|, a) -> abs(a) <| MR.GenD3D10PreMod_NoExcldmovc(bdlt(a, 0), |a|, a) -> dabs(a) <| MR.GenD3D10PreMod_NoExclbreaka match <| MR.GenD3D10PostMod_Bothcontinuea match <| MR.GenD3D10PostMod_Bothreturna match <| MR.GenD3D10PostMod_Bothif(bult(0,x)) -> if(x) <| MR.GenD3D10PostMod_Bothif(bilt(0,x)) -> if(x) <| MR.GenD3D10PostMod_Bothif(bieq(x,0)) -> ifn(x) <| MR.GenD3D10PostMod_Bothif(bine(x,0)) -> if(x) <| MR.GenD3D10PostMod_Bothif(!a) -> ifn(a) <| MR.GenD3D10PostMod_Bothbfi(w, 0i, v, r) : if( width_is_zero(w,r) && allbutwidth_is_zero(w, v) -> iadd(v, r) <| MR.GenD3D10PostMod_Bothor(a, b) : if( and_is_zero(a, b) ) -> iadd(a, b) <| MR.GenD3D10PostMod_Bothdiv(a,b)->mul(a, rcp(b)) <| MR.Gen_RequiredTranslatelt(a, b) -> cmp(a - b, 0f, 1f) <| MR.Gen_RequiredTranslatege(a, b) -> cmp(a - b, 1f, 0f) <| MR.Gen_RequiredTranslatemax(a, -a) -> abs <| MR.Gen_RequiredTranslatemax(a, b) -> cmp(a - b, a, b) <| MR.Gen_RequiredTranslatemin(a, b) -> cmp(a - b, b, a) <| MR.Gen_RequiredTranslatedmad -> dmul, dadd <| MR.Gen_RequiredTranslatecountbits(i) -> and/shift/add sequence <| MR.Gen_RequiredTranslatefirstbitlow(i) -> shift/bine/add sequence <| MR.Gen_RequiredTranslatefirstbit_shi(i) -> shift/bine/add sequence <| MR.Gen_RequiredTranslatefirstbit_hi(i) -> shift/bine/add sequence <| MR.Gen_RequiredTranslatereversebits(i) -> and/shift/or sequence <| MR.Gen_RequiredTranslatef32tof16(i) -> conversion sequence <| MR.Gen_RequiredTranslatef16tof32(i) -> conversion sequence <| MR.Gen_RequiredTranslateubfe(i) -> extraction sequence <| MR.Gen_RequiredTranslateibfe(i) -> extraction sequence <| MR.Gen_RequiredTranslatebfi(i) -> insertion sequence <| MR.Gen_RequiredTranslatepreshader abs -> max(i, neg(i)) <| MR.Gen_RequiredTranslate_Preshaderpreshader sat -> min(max(i, 0), 1) <| MR.Gen_RequiredTranslate_Preshadercmp sequence 1 -> sat <| MR.Gen_OptimizeEarlyTranslate_SAT_NoExclcmp sequence 2 -> sat <| MR.Gen_OptimizeEarlyTranslate_SAT_NoExclpos cmp sequence -> sat <| MR.Gen_OptimizeEarlyTranslate_SAT_NoExclmax(i, neg(i)) -> abs <| MR.Gen_OptimizeEarlyTranslate_SAT_NoExcldmax(i, dneg(i)) -> dabs <| MR.Gen_OptimizeEarlyTranslate_SAT_NoExclcmp (a, a, -a) -> abs <| MR.Gen_OptimizeEarlyTranslate_SAT_NoExclmin 1/max 0 -> sat <| MR.Gen_OptimizeEarlyTranslate_SAT_Exclmax 0/min 1 -> sat <| MR.Gen_OptimizeEarlyTranslate_SAT_Excldmin 1/dmax 0 -> dsat <| MR.Gen_OptimizeEarlyTranslate_SAT_Excldmax 0/dmin 1 -> dsat <| MR.Gen_OptimizeEarlyTranslate_SAT_Excl(n & a) | r : if( known_bfi_bitmask_noshift(n,a,r) && and_is_zero(n,r) ) -> bfi(bfi_bitwidth_noshift(n,a,r), 0i, a, r) <| MR.GenD3D10_OptimizeEarlyTranslate_Excl(a & n) | r : if( known_bfi_bitmask_noshift(n,a,r) && and_is_zero(n,r) ) -> bfi(bfi_bitwidth_noshift(n,a,r), 0i, a, r) <| MR.GenD3D10_OptimizeEarlyTranslate_Exclr | (n & a) : if( known_bfi_bitmask_noshift(n,a,r) && and_is_zero(n,r) ) -> bfi(bfi_bitwidth_noshift(n,a,r), 0i, a, r) <| MR.GenD3D10_OptimizeEarlyTranslate_Exclr | (a & n) : if( known_bfi_bitmask_noshift(n,a,r) && and_is_zero(n,r) ) -> bfi(bfi_bitwidth_noshift(n,a,r), 0i, a, r) <| MR.GenD3D10_OptimizeEarlyTranslate_Excla | r : if( known_bfi_bitmask_noshift_impmask(a,r) && and_is_zero(a,r) ) -> bfi(bfi_bitwidth_noshift_impmask(a,r), 0i, a, r) <| MR.GenD3D10_OptimizeEarlyTranslate_Exclr | a : if( known_bfi_bitmask_noshift_impmask(a,r) && and_is_zero(a,r) ) -> bfi(bfi_bitwidth_noshift_impmask(a,r), 0i, a, r) <| MR.GenD3D10_OptimizeEarlyTranslate_Excl((a << m) & n) | i : if( known_bfi_bitmask_postshift_ignore(n,a,m,i) ) -> bfi(bfi_bitwidth_postshift_ignore(n,a,m,i), m, a, 0i) <| MR.GenD3D10_OptimizeEarlyTranslate_Exclimul(a, iv_pow2) -> ishl(a, get_lowest_bit(iv_pow2)) <| MR.GenD3D10_OptimizeEarlyTranslateudiv(a, iv_pow2) -> ushr(a, get_lowest_bit(iv_pow2)) <| MR.GenD3D10_OptimizeEarlyTranslate(a << n) >> (m) -> ibfe(32-m, m-n, a) <| MR.GenD3D10_OptimizeEarlyTranslateb = ubfe/ushr(a,o), movc((b >> o) & iv_pow2, bfi(w, 0, b, -iv_pow2)) -> ibfe(get_first_bit(iv_pow2), 0, a) <| MR.GenD3D10_OptimizeEarlyTranslateb = ubfe/ushr(a,o), movc((a >> o) & iv_pow2, b | -iv_pow2) -> ibfe(get_first_bit(iv_pow2), 0, a) <| MR.GenD3D10_OptimizeEarlyTranslatemovc(b & iv_pow2, bfi(w, 0, b, -iv_pow2), b) -> ibfe(get_first_bit(iv_pow2), 0, b) <| MR.GenD3D10_OptimizeEarlyTranslatemovc(b & iv_pow2, bfi(w, 0, (b & m), -iv_pow2)) -> ibfe(get_first_bit(iv_pow2), 0, (b&m)) <| MR.GenD3D10_OptimizeEarlyTranslatemovc(b & iv_pow2, b | -iv_pow2, b) -> ibfe(get_first_bit(iv_pow2), 0, b) <| MR.GenD3D10_OptimizeEarlyTranslatemovc(b & iv_pow2, (b & m) | -iv_pow2, b) -> ibfe(get_first_bit(iv_pow2), 0, (b&m)) <| MR.GenD3D10_OptimizeEarlyTranslate(a << n) >> (m) -> ubfe(32-m, m-n, a) <| MR.GenD3D10_OptimizeEarlyTranslate(a & ((iv_pow2 << n) - 1)) -> bfi(iv_pow2 + n, 0, a, 0i) <| MR.GenD3D10_OptimizeEarlyTranslate(a & ~((iv_pow2 << n) - 1)) -> bfi(iv_pow2 + n, 0, 0, a) <| MR.GenD3D10_OptimizeEarlyTranslate(a & ~(((iv_pow2 << n) - 1) << o) -> bfi(iv_pow2 + n, o, 0, a) <| MR.GenD3D10_OptimizeEarlyTranslate(a & ~(((iv_pow2 << n) << ov) + (-1 << ov))) -> bfi(iv_pow2 + n, ov, 0, a) <| MR.GenD3D10_OptimizeEarlyTranslate((a >> o1) << o2) : if( o1 == o2 ) -> bfi(o, 0, 0, a) <| MR.GenD3D10_OptimizeEarlyTranslate(a | ((iv_pow2 << n) - 1)) -> bfi(iv_pow2 + n, 0, -1, a) <| MR.GenD3D10_OptimizeEarlyTranslate(a | (((iv_pow2 << n) - 1) << o)) -> bfi(iv_pow2 + n, o, -1, a) <| MR.GenD3D10_OptimizeEarlyTranslate(a | (((iv_pow2 << n) << ov) + (-1 << ov))) -> bfi(iv_pow2 + n, ov, -1, a) <| MR.GenD3D10_OptimizeEarlyTranslate(a | (b << n)) : if(known_bfi_bitwidth_impmask(a, b, n)) -> bfi(get_bfi_bitwidth_impmask(a, b, n), n, b, a) <| MR.GenD3D10_OptimizeEarlyTranslate(a & n) << m : if( known_bfi_bitmask(a,n,m) ) -> bfi(bfi_bitwidth(a,n,m), m, n, 0i) <| MR.GenD3D10_OptimizeEarlyTranslate(a & n) | i << m : if( known_bfi_bitmask_ignore(a,n,i,m) ) -> bfi(bfi_bitwidth_ignore(a,n,i,m), m, n | i, 0i) <| MR.GenD3D10_OptimizeEarlyTranslate(a & n) << m : if( known_bfi_bitmask(n,a,m) ) -> bfi(bfi_bitwidth(n,a,m), m, a, 0i) <| MR.GenD3D10_OptimizeEarlyTranslate(a << m) & n : if( known_bfi_bitmask_postshift(n,a,m) ) -> bfi(bfi_bitwidth_postshift(n,a,m), m, a, 0i) <| MR.GenD3D10_OptimizeEarlyTranslate(a & n) >> m : if( known_ubfe_bitmask(a,n,m) ) -> ubfe(ubfe_bitwidth(a,n,m), m, n) <| MR.GenD3D10_OptimizeEarlyTranslate(a & n) >> m : if( known_ubfe_bitmask(n,a,m) ) -> ubfe(bitwidth(n,a,m), m, a) <| MR.GenD3D10_OptimizeEarlyTranslate(int)(a & n) >> m : if( high_bit_clear(a & n) && known_ubfe_bitmask(a,n,m) ) -> ubfe(bitwidth(a,n,m), m, n) <| MR.GenD3D10_OptimizeEarlyTranslate(int)(a & n) >> m : if( high_bit_clear(a & n) && known_ubfe_bitmask(n,a,m) ) -> ubfe(ubfe_bitwidth(n,a,m), m, a) <| MR.GenD3D10_OptimizeEarlyTranslate(a >> m) & n : if( known_ubfe_bitmask_nomaskshift(a,n,m) ) -> ubfe(ubfe_bitwidth_nomaskshift(a,n,m), m, n) <| MR.GenD3D10_OptimizeEarlyTranslate(a >> m) & n : if( high_bit_clear(a & n) && known_ubfe_bitmask_nomaskshift(a,n,m) ) -> ubfe(ubfe_bitwidth_nomaskshift(a,n,m), m, n) <| MR.GenD3D10_OptimizeEarlyTranslatedcl_func_output(a) -> o->append_dataflow() <| SMR.DataflowAnalysisloop_in(completed a) -> o->append_inloop() <| SMR.RangeDataAnalysis$IsStandardLoad(a, chain) -> append_addressed(o, chain) (range/flag prop) <| SMR.RangeDataAnalysis$IsResLoad(uav, a, addr, offs, mask) -> append_arg(sources(o, a)) <| SMR.RangeDataAnalysismovc(true,b,c) -> append_arg(b) <| SMR.RangeDataAnalysismovc(false,b,c) -> append_arg(b) <| SMR.RangeDataAnalysismovc(a,b,c) -> append_arg(b, c) <| SMR.RangeDataAnalysiscmp(a,b,c) -> append_arg(b, c) <| SMR.RangeDataAnalysisignore move(a) -> append_arg(a) <| SMR.RangeDataAnalysisignore double move(a) -> append_arg(a) <| SMR.RangeDataAnalysispred move(a) -> append_arg(a) <| SMR.RangeDataAnalysistunnelable move(a) -> append_arg(a) <| SMR.RangeDataAnalysisand(btrue,a) -> append_arg(a) <| SMR.RangeDataAnalysisand(false,a) -> append_arg(0,a) <| SMR.RangeDataAnalysisor(bfalse,a) -> append_arg(a) <| SMR.RangeDataAnalysisor(true,a) -> append_arg(true,a) <| SMR.RangeDataAnalysismul(1f,a) -> append_arg(a) <| SMR.RangeDataAnalysisadd(0f,a) -> append_arg(a) <| SMR.RangeDataAnalysismul(fbool,a) -> append_arg(0f,a) <| SMR.RangeDataAnalysismul(fbool,finite a) -> append_arg(0f,a) <| SMR.RangeDataAnalysislerp(fbool, a, b) -> append_arg(a,b) <| SMR.RangeDataAnalysislerp(fbool, finite a, finite b) -> append_arg(a,b) <| SMR.RangeDataAnalysislerp(fbool, a, 0) -> append_arg(a,0) <| SMR.RangeDataAnalysislerp(fbool, finite a, 0) -> append_arg(a,0) <| SMR.RangeDataAnalysisa + -a -> append_arg(0) <| SMR.RangeDataAnalysis(a + F) - a -> append_arg(F) <| SMR.RangeDataAnalysisa + (F - a) -> append_arg(F) <| SMR.RangeDataAnalysis(a + F1) - (a + F2) -> append_arg(F1-F2) <| SMR.RangeDataAnalysisfinite a + -a -> append_arg(0) <| SMR.RangeDataAnalysisi + -i -> append_arg(0) <| SMR.RangeDataAnalysis(i + I) - i -> append_arg(I) <| SMR.RangeDataAnalysisi + (I - i) -> append_arg(I) <| SMR.RangeDataAnalysis(i + I1) - (i + I2) -> append_arg(I1-I2) <| SMR.RangeDataAnalysisendif(a,b) -> append_arg(a,b) <| SMR.RangeDataAnalysis$IsMultiWriteOut(a, chain) -> append_sources(a) <| SMR.RangeDataAnalysisbind_load(chain, value) -> o->append_sources(chain) <| SMR.DataFlagAnalysiso = dfuse(ab) -> o->append_dfuse() <| SMR.DataFlagAnalysisloop_in(completed a) -> o->append_inloop() <| SMR.DataFlagAnalysisloop_endif(a) -> append_arg(a, pred_a) <| SMR.DataFlagAnalysisfunction_endif(a) -> append_arg(a, pred_a) <| SMR.DataFlagAnalysiscl = $IsBreak(a, ci) -> append_arg(a, ci) <| SMR.DataFlagAnalysiscl = $IsContinue(a, ci) -> append_arg(a, ci) <| SMR.DataFlagAnalysiscf = $IsReturn(a, ci) -> append_arg(a, ci) <| SMR.DataFlagAnalysiscl = $IsConsume(a, b, ci) -> append_arg(ci) <| SMR.DataFlagAnalysisendif(a,b) -> append_arg(a,b,p_a) <| SMR.DataFlagAnalysisloop_endif(a,b) -> append_arg(a,b,p_a) <| SMR.DataFlagAnalysisfunction_endif(a,b) -> append_arg(a,b,p_a) <| SMR.DataFlagAnalysischain_merge($IsSync() || chain) -> append_arg(sync) <| SMR.DataFlagAnalysis_ConstInterp$IsStandardLoad(a, chain) -> append_addressed(o, chain), append_arg(a, chain) <| SMR.DataFlagAnalysis_PlaceHolder$IsAtomicAllocConsume(a, res) -> append_arg(all_sources(o, a)) <| SMR.DataFlagAnalysis_PlaceHolder$IsTwoValueAtomic(chain, res, addr, op1, op2) -> append_arg(all_sources(o, chain), chain, addr, op1, op2) <| SMR.DataFlagAnalysis_PlaceHolder$IsBasicOrImmAtomic(a, res, addr, op) -> append_arg(all_sources(o, a), a, addr, op) <| SMR.DataFlagAnalysis_PlaceHolder$IsResLoad(uav, a, addr, offs, mask) -> append_arg(all_sources(o, a), uav, a, addr, offs, mask) <| SMR.DataFlagAnalysis_PlaceHolder$IsStandardStore(addr, val, chain) -> append_param(chain) <| SMR.DataFlagAnalysis_PlaceHolder$IsResStore(uav, a, addr, offs, mask, val) -> append_param(a) <| SMR.DataFlagAnalysis_PlaceHoldercl = endcase(ci, ch) -> append_arg(ci, ci_p, ch) <| SMR.DataFlagAnalysis_PlaceHoldercl = fcbody_end(ci, ch) -> append_arg(ci, ci_p, ch) <| SMR.DataFlagAnalysis_PlaceHolderdiscard_endif(a,b) -> append_arg(a,b,p_a) <| SMR.DataFlagAnalysis_PlaceHolder$IsLoop(a) -> append_sources() (loop predicate linkage) <| SMR.DataFlagAnalysis_PlaceHolder$IsMultiWriteOut(a, chain) -> append_sources(a) <| SMR.DataFlagAnalysis_PlaceHolder$IsSync() -> append_all_visible+inputs(UAV chain args) <| SMR.DataFlagAnalysis_PlaceHolder$IsStandardStore(addr, val, chain) -> append_param(chain) <| SMR.DataFlagAnalysis_NoPlaceHolderchain_merge($IsSync() || chain) -> append_arg(chain) <| SMR.DataFlagAnalysis_NoPlaceHolderchain_merge(chain_merge() || chain) -> append_arg(chain) <| SMR.DataFlagAnalysis_NoPlaceHolderarray_merge(chain_merge() || chain) -> append_arg(chain) <| SMR.DataFlagAnalysis_NoPlaceHoldercl = emitarg(a, b, ci) -> append_arg(ci) <| SMR.DataFlagAnalysis_NoPlaceHoldercl = emit(ci, stream) -> append_arg(ci) <| SMR.DataFlagAnalysis_NoPlaceHoldercl = casecond(ci, c) -> append_arg(ci) <| SMR.DataFlagAnalysis_NoPlaceHoldercl = endcase(ci, ch) -> append_arg(ci) <| SMR.DataFlagAnalysis_NoPlaceHoldercl = fcbody(ci, c) -> append_arg(ci, c) <| SMR.DataFlagAnalysis_NoPlaceHoldercl = fcbody_end(ci, ch) -> append_arg(ci, ci_p, ch) <| SMR.DataFlagAnalysis_NoPlaceHolderloop(a) -> append_sources() (loop predicate linkage) <| SMR.DataFlagAnalysis_NoPlaceHoldero = $IsStandardLoad(a, chain) -> append_addressed(o, chain) (all sources) <| SMR.DataFlagAnalysis_NoPlaceHolder$IsMultiWriteOut(a, chain) -> append_sources(a) <| SMR.DataFlagAnalysis_NoPlaceHolder$IsAtomicAllocConsume(a, res) -> append_arg(all_sources(o, a)) <| SMR.DataFlagAnalysis_NoPlaceHolder$IsTwoValueAtomic(chain, res, addr, op1, op2) -> append_arg(chain, addr, op1, op2) <| SMR.DataFlagAnalysis_NoPlaceHolder$IsBasicOrImmAtomic(a, res, addr, op) -> append_arg(all_sources(o, a), addr, op) <| SMR.DataFlagAnalysis_NoPlaceHolder$IsResLoad(uav, a, addr, offs, mask) -> append_arg(all_sources(o, a), addr, offs) <| SMR.DataFlagAnalysis_NoPlaceHolder$IsResStore(uav, a, addr, offs, mask, val) -> append_param(a) (chain) <| SMR.DataFlagAnalysis_NoPlaceHolderd(x)/dz -> dx/dz <| SR.GenDerivatives_Unaryd((double)x)/dz -> (double)dx/dz <| SR.GenDerivatives_Unaryd(-x)/dz -> -dx/dz <| SR.GenDerivatives_Unaryd((double)-x)/dz -> -(double)dx/dz <| SR.GenDerivatives_Unaryd(x+eps)/dz -> dx/dz <| SR.GenDerivatives_Unaryd(x^-0.5)/dz -> -0.5*x^-1.5 * dx/dz <| SR.GenDerivatives_Unaryd(frac(x))/dz -> dx/dz <| SR.GenDerivatives_Unaryd(2^x)/dz -> ln(2) * 2^x * dx/dz <| SR.GenDerivatives_Unaryd(log_2(x))/dz -> 1/(x * ln(2)) * dx/dz <| SR.GenDerivatives_Unarysqrt(x)/dz -> 0.5 / sqrt(x) * (dx/dz) <| SR.GenDerivatives_Unaryfloat d(1/x)/dz -> -dx/dz/x^2 <| SR.GenDerivatives_Unarydouble d(1/x)/dz -> -dx/dz/x^2 <| SR.GenDerivatives_Unaryd(IsRound(x))/dz -> 0 <| SR.GenDerivatives_Unaryd(sin(x))/dz -> cos(x) * dx/dz <| SR.GenDerivatives_Unaryd(cos(x))/dz -> -sin(x) * dx/dz <| SR.GenDerivatives_Unaryd(asin(x))/dz -> 1/sqrt(1-x^2) * dx/dz <| SR.GenDerivatives_Unaryd(acos(x))/dz -> -1/sqrt(1-x^2) * dx/dz <| SR.GenDerivatives_Unaryd(atan(x))/dz -> 1/(1+x^2) * dx/dz <| SR.GenDerivatives_Unary$IsAnyDeriv(x)/dz -> $IsAnyDeriv(dx/dz) <| SR.GenDerivatives_Unarydsy(x)/dz -> dsy(dx/dz) <| SR.GenDerivatives_Unarydtof(x)/dz -> dtof(dx/dz) <| SR.GenDerivatives_Unaryftod(x)/dz -> ftod(dx/dz) <| SR.GenDerivatives_Unaryd(IsIntToFloat(x))/dz -> 0f <| SR.GenDerivatives_Unaryd(IsIntToDouble(x))/dz -> 0lf <| SR.GenDerivatives_Unaryd(min(x,y))/dz -> (x < y) ? dx/dz : ((y < x) ? dy/dz : min(dx/dz, dy/dz) <| SR.GenDerivatives_Binaryd(max(x,y))/dz -> (x > y) ? dx/dz : ((y > x) ? dy/dz : max(dx/dz, dy/dz) <| SR.GenDerivatives_Binaryd(dmin(x,y))/dz -> (x < y) ? dx/dz : ((y < x) ? dy/dz : dmin(dx/dz, dy/dz) <| SR.GenDerivatives_Binaryd(dmax(x,y))/dz -> (x > y) ? dx/dz : ((y > x) ? dy/dz : dmax(dx/dz, dy/dz) <| SR.GenDerivatives_Binaryd(x + y)/dz -> dx/dz + dy/dz <| SR.GenDerivatives_Binaryd((double)x + (double)y)/dz -> dx/dz + dy/dz <| SR.GenDerivatives_Binaryd(x * x)/dz -> 2*dx/dz * x <| SR.GenDerivatives_Binaryd((double)x * x)/dz -> 2*dx/dz * x <| SR.GenDerivatives_Binaryd(x * y)/dz -> dx/dz * y + x * dy/dz <| SR.GenDerivatives_Binaryd((double)x * y)/dz -> dx/dz * y + x * dy/dz <| SR.GenDerivatives_Binaryd(atan2(x,y))/dz -> 1 / (1 + (y/x)^2) * d(y/x)/dz <| SR.GenDerivatives_Binaryd(x / y)/dz -> dx/dz / y + x * -dy/dz / y^2 <| SR.GenDerivatives_Binaryd(a ? b : c)/dz -> a ? db/dz : dc/dz <| SR.GenDerivatives_Ternaryabs fp_flags <| SFPSabs fp_specials <| SFPSabs float_literal <| SFPSabs fp_range <| SFPSacos fp_flags <| SFPSacos fp_specials <| SFPSacos float_literal <| SFPSacos fp_range <| SFPSadd fp_flags <| SFPSadd float_literal <| SFPSadd fp_range <| SFPSand fp_flags <| SFPSand int_flags <| SFPSand int_literal <| SFPSand bits_known <| SFPSasin fp_flags <| SFPSasin fp_specials <| SFPSasin float_literal <| SFPSasin fp_range <| SFPSatan fp_flags <| SFPSatan fp_specials <| SFPSatan float_literal <| SFPSatan fp_range <| SFPSatan2 fp_flags <| SFPSatan2 fp_specials <| SFPSatan2 float_literal <| SFPSatan2 fp_range <| SFPSbdeq fp_flags <| SFPSbdeq int_literal <| SFPSbdeq int_range <| SFPSbdge fp_flags <| SFPSbdge int_literal <| SFPSbdge int_range <| SFPSbdlt fp_flags <| SFPSbdlt int_literal <| SFPSbdlt int_range <| SFPSbdne fp_flags <| SFPSbdne int_literal <| SFPSbdne int_range <| SFPSbeq fp_flags <| SFPSbeq int_literal <| SFPSbeq int_range <| SFPSbfi fp_flags <| SFPSbfi int_literal <| SFPSbfi bits_known <| SFPSbge fp_flags <| SFPSbge int_literal <| SFPSbge int_range <| SFPSblt fp_flags <| SFPSblt int_literal <| SFPSblt int_range <| SFPSbne fp_flags <| SFPSbne int_literal <| SFPSbne int_range <| SFPSbieq fp_flags <| SFPSbieq int_literal <| SFPSbieq bits_known <| SFPSbieq int_range <| SFPSbige fp_flags <| SFPSbige int_literal <| SFPSbige bits_known <| SFPSbige int_range <| SFPSbilt fp_flags <| SFPSbilt int_literal <| SFPSbilt bits_known <| SFPSbilt int_range <| SFPSbine fp_flags <| SFPSbine int_literal <| SFPSbine bits_known <| SFPSbine int_range <| SFPSbufinfo fp_flags <| SFPSbuge fp_flags <| SFPSbuge int_literal <| SFPSbuge bits_known <| SFPSbuge int_range <| SFPSbult fp_flags <| SFPSbult int_literal <| SFPSbult bits_known <| SFPSbult int_range <| SFPSbreak fp_flags <| SFPSbtof fp_flags <| SFPSbtoi fp_flags <| SFPSbtoi int_literal <| SFPSbtoi bits_known <| SFPSbtoi int_range <| SFPScalclod1d fp_flags <| SFPScalclod1d_a fp_flags <| SFPScalclod1d_u fp_flags <| SFPScalclod1d_u_a fp_flags <| SFPScalclod2d fp_flags <| SFPScalclod2d_a fp_flags <| SFPScalclod2d_u fp_flags <| SFPScalclod2d_u_a fp_flags <| SFPScalclod3d fp_flags <| SFPScalclod3d_u fp_flags <| SFPScalclodcube fp_flags <| SFPScalclodcube_a fp_flags <| SFPScalclodcube_u fp_flags <| SFPScalclodcube_u_a fp_flags <| SFPScase fp_flags <| SFPSceil fp_flags <| SFPSceil fp_specials <| SFPSceil float_literal <| SFPSceil fp_range <| SFPSchain_end fp_flags <| SFPScmp fp_flags <| SFPScmp fp_specials <| SFPScmp float_literal <| SFPScmp fp_range <| SFPScontinue fp_flags <| SFPScos fp_flags <| SFPScos fp_specials <| SFPScos float_literal <| SFPScos fp_range <| SFPScountbits fp_flags <| SFPScountbits int_literal <| SFPScountbits bits_known <| SFPSdabs fp_flags <| SFPSdabs fp_specials <| SFPSdabs float_literal <| SFPSdabs fp_range <| SFPSdadd fp_flags <| SFPSdadd float_literal <| SFPSdadd fp_range <| SFPSdfma fp_flags <| SFPSdfma fp_specials <| SFPSdfuse fp_flags <| SFPSdfuse float_literal <| SFPSdfuse fp_specials <| SFPSdmad fp_flags <| SFPSdmad fp_specials <| SFPSdmad float_literal <| SFPSdmad fp_range <| SFPSdmax fp_flags <| SFPSdmax fp_specials <| SFPSdmax float_literal <| SFPSdmax fp_range <| SFPSdmin fp_flags <| SFPSdmin fp_specials <| SFPSdmin float_literal <| SFPSdmin fp_range <| SFPSdmov fp_flags <| SFPSdmov mov <| SFPSdmovc fp_flags <| SFPSdmovc fp_specials <| SFPSdmovc float_literal <| SFPSdmul fp_flags <| SFPSdmul float_literal <| SFPSdmul fp_range <| SFPSdneg fp_flags <| SFPSdneg fp_specials <| SFPSdneg float_literal <| SFPSdneg fp_range <| SFPSdot fp_flags <| SFPSdot float_literal <| SFPSdot fp_range <| SFPSdsat fp_flags <| SFPSdsat float_literal <| SFPSdsat fp_range <| SFPSddiv fp_flags <| SFPSddiv fp_specials <| SFPSddiv float_literal <| SFPSddiv fp_range <| SFPSdrcp_approx fp_flags <| SFPSdrcp_approx fp_specials <| SFPSdrcp_approx float_literal <| SFPSdrcp_approx fp_range <| SFPSdsplit fp_flags <| SFPSdsplit int_literal <| SFPSdsplit fp_specials <| SFPSdtof fp_flags <| SFPSdtof float_literal <| SFPSdtof fp_range <| SFPSdtof fp_specials <| SFPSdtoi fp_flags <| SFPSdtoi int_literal <| SFPSdtoi int_range <| SFPSdtou fp_flags <| SFPSdtou int_literal <| SFPSdtou int_range <| SFPSdiscardif fp_flags <| SFPSdiv fp_flags <| SFPSdiv fp_specials <| SFPSdiv float_literal <| SFPSdiv fp_range <| SFPSdsx fp_flags <| SFPSdsx fp_specials <| SFPSdsx float_literal <| SFPSdsx fp_range <| SFPSdsy fp_flags <| SFPSdsy fp_specials <| SFPSdsy float_literal <| SFPSdsy fp_range <| SFPSdsx_fine fp_flags <| SFPSdsx_fine fp_specials <| SFPSdsx_fine float_literal <| SFPSdsx_fine fp_range <| SFPSdsy_fine fp_flags <| SFPSdsy_fine fp_specials <| SFPSdsy_fine float_literal <| SFPSdsy_fine fp_range <| SFPSdsx_coarse fp_flags <| SFPSdsx_coarse fp_specials <| SFPSdsx_coarse float_literal <| SFPSdsx_coarse fp_range <| SFPSdsy_coarse fp_flags <| SFPSdsy_coarse fp_specials <| SFPSdsy_coarse float_literal <| SFPSdsy_coarse fp_range <| SFPSeval_centroid fp_flags <| SFPSeval_sample fp_flags <| SFPSeval_snapped fp_flags <| SFPSexp fp_flags <| SFPSexp fp_specials <| SFPSexp float_literal <| SFPSexp fp_range <| SFPSf16tof32 fp_flags <| SFPSf16tof32 float_literal <| SFPSf16tof32 bits_known <| SFPSf32tof16 fp_flags <| SFPSf32tof16 int_literal <| SFPSf32tof16 int_range <| SFPSfcall fp_flags <| SFPSfcbody fp_flags <| SFPSfirstbitlow fp_flags <| SFPSfirstbitlow int_literal <| SFPSfirstbitlow bits_known <| SFPSfirstbit_hi fp_flags <| SFPSfirstbit_hi int_literal <| SFPSfirstbit_hi bits_known <| SFPSfirstbit_shi fp_flags <| SFPSfirstbit_shi int_literal <| SFPSfirstbit_shi bits_known <| SFPSfloor fp_flags <| SFPSfloor fp_specials <| SFPSfloor float_literal <| SFPSfloor fp_range <| SFPSfrc fp_flags <| SFPSfrc fp_specials <| SFPSfrc float_literal <| SFPSfrc fp_range <| SFPSftob fp_flags <| SFPSftob int_literal <| SFPSftob int_range <| SFPSftod fp_flags <| SFPSftod float_literal <| SFPSftod fp_range <| SFPSftod fp_specials <| SFPSftoi fp_flags <| SFPSftoi int_literal <| SFPSftoi int_range <| SFPSftou fp_flags <| SFPSftou int_literal <| SFPSftou int_range <| SFPSfunctionif fp_flags <| SFPSgather2d fp_flags <| SFPSgather2d_a fp_flags <| SFPSgather2d_a_o fp_flags <| SFPSgather2d_o fp_flags <| SFPSgathercube fp_flags <| SFPSgathercube_a fp_flags <| SFPSgathercube_c fp_flags <| SFPSgathercube_c_a fp_flags <| SFPSge fp_flags <| SFPSge float_literal <| SFPSge fp_range <| SFPSiadd fp_flags <| SFPSiadd int_literal <| SFPSiadd bits_known <| SFPSiadd int_range <| SFPSibfe fp_flags <| SFPSibfe int_literal <| SFPSibfe bits_known <| SFPSidiv fp_flags <| SFPSidiv int_literal <| SFPSidiv bits_known <| SFPSidiv int_range <| SFPSimad fp_flags <| SFPSimad int_literal <| SFPSimad bits_known <| SFPSimad int_range <| SFPSimax fp_flags <| SFPSimax int_literal <| SFPSimax bits_known <| SFPSimax int_range <| SFPSimin fp_flags <| SFPSimin int_literal <| SFPSimin bits_known <| SFPSimin int_range <| SFPSimod fp_flags <| SFPSimod int_literal <| SFPSimod bits_known <| SFPSimod int_range <| SFPSimul fp_flags <| SFPSimul int_literal <| SFPSimul bits_known <| SFPSimul int_range <| SFPSineg fp_flags <| SFPSineg int_literal <| SFPSineg bits_known <| SFPSineg int_range <| SFPSishl fp_flags <| SFPSishl int_literal <| SFPSishl bits_known <| SFPSishr fp_flags <| SFPSishr int_literal <| SFPSishr bits_known <| SFPSitob fp_flags <| SFPSitob int_literal <| SFPSitob bits_known <| SFPSitob int_range <| SFPSitod fp_flags <| SFPSitof fp_flags <| SFPSload fp_flags <| SFPSload_o fp_flags <| SFPSload_s fp_flags <| SFPSload_o_s fp_flags <| SFPSload_uav_s fp_flags <| SFPSload_uav fp_flags <| SFPStload fp_flags <| SFPSload2d_msaa fp_flags <| SFPSload2d_msaa_o fp_flags <| SFPSload2d_msaa_o_s fp_flags <| SFPSload2darray_msaa fp_flags <| SFPSload2darray_msaa_o fp_flags <| SFPSload2darray_msaa_o_s fp_flags <| SFPSlog fp_flags <| SFPSlog fp_specials <| SFPSlog float_literal <| SFPSlog fp_range <| SFPSloopif fp_flags <| SFPSlt fp_flags <| SFPSlt float_literal <| SFPSlt fp_range <| SFPSmad fp_flags <| SFPSmad fp_specials <| SFPSmad float_literal <| SFPSmad fp_range <| SFPSmax fp_flags <| SFPSmax fp_specials <| SFPSmax float_literal <| SFPSmax fp_range <| SFPSmin fp_flags <| SFPSmin fp_specials <| SFPSmin float_literal <| SFPSmin fp_range <| SFPSmov fp_flags <| SFPSmov mov <| SFPSmovc fp_flags <| SFPSmovc fp_specials <| SFPSmovc float_literal <| SFPSmsad fp_flags <| SFPSmsad int_literal <| SFPSmsad bits_known <| SFPSmsad int_range <| SFPSmul fp_flags <| SFPSmul float_literal <| SFPSmul fp_range <| SFPSneg fp_flags <| SFPSneg fp_specials <| SFPSneg float_literal <| SFPSneg fp_range <| SFPSnot fp_flags <| SFPSnot int_literal <| SFPSnot bits_known <| SFPSor fp_flags <| SFPSor int_flags <| SFPSor int_literal <| SFPSor bits_known <| SFPSplacement_mov fp_flags <| SFPSplacement_mov mov <| SFPSrcp fp_flags <| SFPSrcp fp_specials <| SFPSrcp float_literal <| SFPSrcp fp_range <| SFPSrcp_approx fp_flags <| SFPSrcp_approx fp_specials <| SFPSrcp_approx float_literal <| SFPSrcp_approx fp_range <| SFPSresinfo fp_flags <| SFPSresinfo_uint fp_flags <| SFPSreturn fp_flags <| SFPSreversebits fp_flags <| SFPSreversebits int_literal <| SFPSreversebits bits_known <| SFPSround fp_flags <| SFPSround fp_specials <| SFPSround float_literal <| SFPSround fp_range <| SFPSrsq fp_flags <| SFPSrsq fp_specials <| SFPSrsq float_literal <| SFPSrsq fp_range <| SFPSsample1d fp_flags <| SFPSsample1d_a fp_flags <| SFPSsample1d_o fp_flags <| SFPSsample1d_a_o fp_flags <| SFPSsample1d_bias fp_flags <| SFPSsample1d_bias_a fp_flags <| SFPSsample1d_bias_o fp_flags <| SFPSsample1d_bias_a_o fp_flags <| SFPSsample1d_bias_l fp_flags <| SFPSsample1d_c fp_flags <| SFPSsample1d_c_a fp_flags <| SFPSsample1d_c_o fp_flags <| SFPSsample1d_c_a_o fp_flags <| SFPSsample1d_c_lz fp_flags <| SFPSsample1d_c_lz_a fp_flags <| SFPSsample1d_c_lz_o fp_flags <| SFPSsample1d_c_lz_a_o fp_flags <| SFPSsample1d_dd fp_flags <| SFPSsample1d_dd_a fp_flags <| SFPSsample1d_dd_o fp_flags <| SFPSsample1d_dd_a_o fp_flags <| SFPSsample1d_lod fp_flags <| SFPSsample1d_lod_a fp_flags <| SFPSsample1d_lod_o fp_flags <| SFPSsample1d_lod_a_o fp_flags <| SFPSsample1d_lod_l fp_flags <| SFPSsample2d fp_flags <| SFPSsample2d_a fp_flags <| SFPSsample2d_o fp_flags <| SFPSsample2d_a_o fp_flags <| SFPSsample2d_dd fp_flags <| SFPSsample2d_dd_a fp_flags <| SFPSsample2d_dd_o fp_flags <| SFPSsample2d_dd_a_o fp_flags <| SFPSsample2d_lod fp_flags <| SFPSsample2d_lod_a fp_flags <| SFPSsample2d_lod_o fp_flags <| SFPSsample2d_lod_a_o fp_flags <| SFPSsample2d_c fp_flags <| SFPSsample2d_c_a fp_flags <| SFPSsample2d_c_o fp_flags <| SFPSsample2d_c_a_o fp_flags <| SFPSsample2d_c_lz fp_flags <| SFPSsample2d_c_lz_a fp_flags <| SFPSsample2d_c_lz_o fp_flags <| SFPSsample2d_c_lz_a_o fp_flags <| SFPSsample2d_bias fp_flags <| SFPSsample2d_bias_a fp_flags <| SFPSsample2d_bias_o fp_flags <| SFPSsample2d_bias_a_o fp_flags <| SFPSsample2d_lod_l fp_flags <| SFPSsample2d_bias_l fp_flags <| SFPSsample3d fp_flags <| SFPSsample3d_o fp_flags <| SFPSsample3d_dd fp_flags <| SFPSsample3d_dd_o fp_flags <| SFPSsample3d_lod fp_flags <| SFPSsample3d_lod_o fp_flags <| SFPSsample3d_bias fp_flags <| SFPSsample3d_bias_o fp_flags <| SFPSsample3d_lod_l fp_flags <| SFPSsample3d_bias_l fp_flags <| SFPSsamplecube fp_flags <| SFPSsamplecube_dd fp_flags <| SFPSsamplecube_lod fp_flags <| SFPSsamplecube_c fp_flags <| SFPSsamplecube_c_a fp_flags <| SFPSsamplecube_c_lz fp_flags <| SFPSsamplecube_c_lz_a fp_flags <| SFPSsamplecube_bias fp_flags <| SFPSsamplecube_a fp_flags <| SFPSsamplecube_dd_a fp_flags <| SFPSsamplecube_lod_a fp_flags <| SFPSsamplecube_bias_a fp_flags <| SFPSsamplecube_lod_l fp_flags <| SFPSsamplecube_bias_l fp_flags <| SFPSsampleinfo fp_flags <| SFPSsampleinfo_uint fp_flags <| SFPSsampleinfo_rt fp_flags <| SFPSsampleinfo_uint_rt fp_flags <| SFPSsamplepos fp_flags <| SFPSsamplepos_rt fp_flags <| SFPSgather2d_a_o_s fp_flags <| SFPSgather2d_o_s fp_flags <| SFPSgathercube_a_s fp_flags <| SFPSgathercube_c_a_s fp_flags <| SFPSgathercube_c_s fp_flags <| SFPSgathercube_s fp_flags <| SFPSsample1d_a_o_cl_s fp_flags <| SFPSsample1d_bias_a_o_cl_s fp_flags <| SFPSsample1d_bias_o_cl_s fp_flags <| SFPSsample1d_c_a_o_cl_s fp_flags <| SFPSsample1d_c_lz_a_o_s fp_flags <| SFPSsample1d_c_lz_o_s fp_flags <| SFPSsample1d_c_o_cl_s fp_flags <| SFPSsample1d_dd_a_o_cl_s fp_flags <| SFPSsample1d_dd_o_cl_s fp_flags <| SFPSsample1d_lod_a_o_s fp_flags <| SFPSsample1d_lod_o_s fp_flags <| SFPSsample1d_o_cl_s fp_flags <| SFPSsample2d_a_o_cl_s fp_flags <| SFPSsample2d_bias_a_o_cl_s fp_flags <| SFPSsample2d_bias_o_cl_s fp_flags <| SFPSsample2d_c_a_o_cl_s fp_flags <| SFPSsample2d_c_lz_a_o_s fp_flags <| SFPSsample2d_c_lz_o_s fp_flags <| SFPSsample2d_c_o_cl_s fp_flags <| SFPSsample2d_dd_a_o_cl_s fp_flags <| SFPSsample2d_dd_o_cl_s fp_flags <| SFPSsample3d_dd_o_cl_s fp_flags <| SFPSsample2d_lod_a_o_s fp_flags <| SFPSsample2d_lod_o_s fp_flags <| SFPSsample2d_o_cl_s fp_flags <| SFPSsample3d_bias_o_cl_s fp_flags <| SFPSsample3d_lod_o_s fp_flags <| SFPSsample3d_o_cl_s fp_flags <| SFPSsamplecube_a_cl_s fp_flags <| SFPSsamplecube_bias_a_cl_s fp_flags <| SFPSsamplecube_bias_cl_s fp_flags <| SFPSsamplecube_c_a_cl_s fp_flags <| SFPSsamplecube_c_cl_s fp_flags <| SFPSsamplecube_c_lz_a_s fp_flags <| SFPSsamplecube_c_lz_s fp_flags <| SFPSsamplecube_cl_s fp_flags <| SFPSsamplecube_dd_a_cl_s fp_flags <| SFPSsamplecube_dd_cl_s fp_flags <| SFPSsamplecube_lod_a_s fp_flags <| SFPSsamplecube_lod_s fp_flags <| SFPSsat fp_flags <| SFPSsat float_literal <| SFPSsat fp_range <| SFPSsin fp_flags <| SFPSsin fp_specials <| SFPSsin float_literal <| SFPSsin fp_range <| SFPSsincos fp_flags <| SFPSsincos fp_specials <| SFPSsincos float_literal <| SFPSsincos fp_range <| SFPSsqrt fp_flags <| SFPSsqrt fp_specials <| SFPSsqrt float_literal <| SFPSsqrt fp_range <| SFPSswitch fp_flags <| SFPStex1d fp_flags <| SFPStex1d_bias fp_flags <| SFPStex1d_dd fp_flags <| SFPStex1d_lod fp_flags <| SFPStex1d_proj fp_flags <| SFPStex2d fp_flags <| SFPStex2d_bias fp_flags <| SFPStex2d_dd fp_flags <| SFPStex2d_lod fp_flags <| SFPStex2d_proj fp_flags <| SFPStex3d fp_flags <| SFPStex3d_bias fp_flags <| SFPStex3d_dd fp_flags <| SFPStex3d_lod fp_flags <| SFPStex3d_proj fp_flags <| SFPStexcube fp_flags <| SFPStexcube_bias fp_flags <| SFPStexcube_dd fp_flags <| SFPStexcube_lod fp_flags <| SFPStexcube_proj fp_flags <| SFPStrunc fp_flags <| SFPStrunc fp_specials <| SFPStrunc float_literal <| SFPStrunc fp_range <| SFPSuaddc fp_flags <| SFPSuaddc int_literal <| SFPSuaddc bits_known <| SFPSuaddc int_range <| SFPSubfe fp_flags <| SFPSubfe int_literal <| SFPSubfe bits_known <| SFPSusubb fp_flags <| SFPSusubb int_literal <| SFPSusubb bits_known <| SFPSusubb int_range <| SFPSudiv fp_flags <| SFPSudiv int_literal <| SFPSudiv bits_known <| SFPSudiv int_range <| SFPSumax fp_flags <| SFPSumax int_literal <| SFPSumax bits_known <| SFPSumax int_range <| SFPSumin fp_flags <| SFPSumin int_literal <| SFPSumin bits_known <| SFPSumin int_range <| SFPSumod fp_flags <| SFPSumod int_literal <| SFPSumod bits_known <| SFPSumod int_range <| SFPSumul fp_flags <| SFPSumul int_literal <| SFPSumul bits_known <| SFPSumul int_range <| SFPSushr fp_flags <| SFPSushr int_literal <| SFPSushr bits_known <| SFPSutof fp_flags <| SFPSutod fp_flags <| SFPSxor fp_flags <| SFPSxor int_flags <| SFPSxor int_literal <| SFPSxor bits_known <| SFPScheck_access_fully_mapped fp_flags <| SFPSbreak_consume fp_flags <| SFPScontinue_consume fp_flags <| SFPSloopif_consume fp_flags <| SFPSoutput_consume fp_flags <| SFPSreturn_consume fp_flags <| SFPSsync_g fp_flags <| SFPSsync_ug fp_flags <| SFPSsync_up fp_flags <| SFPSsync_g_ug fp_flags <| SFPSsync_g_up fp_flags <| SFPSsync_g_t fp_flags <| SFPSsync_ug_t fp_flags <| SFPSsync_up_t fp_flags <| SFPSsync_g_ug_t fp_flags <| SFPSsync_g_up_t fp_flags <| SFPSatomic_and fp_flags <| SFPSatomic_or fp_flags <| SFPSatomic_xor fp_flags <| SFPSatomic_iadd fp_flags <| SFPSatomic_imax fp_flags <| SFPSatomic_imin fp_flags <| SFPSatomic_umax fp_flags <| SFPSatomic_umin fp_flags <| SFPSatomic_cmp_store fp_flags <| SFPSimm_atomic_and fp_flags <| SFPSimm_atomic_or fp_flags <| SFPSimm_atomic_xor fp_flags <| SFPSimm_atomic_iadd fp_flags <| SFPSimm_atomic_imax fp_flags <| SFPSimm_atomic_imin fp_flags <| SFPSimm_atomic_umax fp_flags <| SFPSimm_atomic_umin fp_flags <| SFPSimm_atomic_exch fp_flags <| SFPSimm_atomic_cmp_exch fp_flags <| SFPSimm_atomic_alloc fp_flags <| SFPSimm_atomic_consume fp_flags <| SFPSNeeds to be replaced with a real ruleinternal warning: optimization did not convergemultiple variables found with the same user-specified locationgradient-based operations must be moved out of flow control to prevent divergence. Performance may improve by using a non-gradient operationcannot have gradient operations inside loops with divergent flow controlinternal error: argument pulled into unrelated predicatecannot have divergent gradient operations inside flow controlinternal error: invalid registerarray index out of bounds <| A%u (B%u), I%u (B%u)variable '%s' used without having been completely initialized <| A%u (B%u), I%u (B%u)thread sync operation must be in non-varying flow control, due to a potential race condition this sync is illegal, consider adding a sync after reading any values controlling shader execution at this pointthread sync operation found in varying flow control, consider reformulating your algorithm so all threads will hit the sync simultaneouslyvaryinggradient operation uses a value that may not be defined for all pixels (in %s UAV loads can not participate in gradient operations)UAV-relatedfloating point division by zeroimaginary square rootindefinite logarithmindefinite arcsineindefinite arccosinedouble-precision floating point division by zeroLiteral floating-point value out of integer range for conversion: %fLiteral floating-point value out of unsigned range for conversion: %fsum of %g and %g cannot be represented accurately in double precisionInteger divide by zeroUnsigned integer divide by zerofloating-point value out of integer range for conversion: %ffloating-point value out of unsigned range for conversion: %findefinite derivative calculationPossible integer divide by zeroQQQQQQQQQQQQQQQQQQQQQ/P/P/P/P/P/P/P/P/P/P'''}~'{|'z tuvwxymnopqMrNsOfghijMkNlOabcde[\]^_`UVWXYZOPQRSTIJKLMNCDEFGH=>?@AB89:;%<&234567()*+,-./01%&'"#$ !

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*)	Reading from texture buffers is unsupported on %stvShader uses texture addressing operations in a dependency chain that is too complex for the target shader model (%s) to handle.internal error: instruction list too longinternal error: instruction list and count mismatchnote that in IEEE strict mode, all values are implicitly marked precisevariable '%s' has a minimum precision type and cannot be marked precise <| A%u (B%u)expression has a minimum precision type and cannot be marked precise <| A%u (B%u), I%u (B%u)internal error: compiler-generated value has a minimum precision type and is marked precise <| A%u (B%u)internal error: argument used without having been initialized <| A%u (B%u), I%u (B%u)internal error: output argument was never initialized <| (A%u (B%u))internal error: cannot write to argument pool <| (A%u (B%u), I%u (B%u))internal error: cannot read from argument pool <| (A%u (B%u))internal error: 64-bit arg component %u not aligned <| A%u (B%u)internal error: reading from value known not to be read <| (A%u (B%u))internal error: argument was never used <| (A%u (B%u), I%u (B%u))internal error: argument was never used <| (A%u (B%u))use of potentially uninitialized variable (%s)infinite loop detected - loop never exitsarray index out of boundsInternal error: unpredicated endif inputInternal error: invalid read of more specific predicateinternal error: unpredicated incompleteinternal error: unpredicated loop_inInternal error: unread predicatepreshaderoverlapping register semantics not yet implemented 'c%u'internal error: component out of rangeSV_TARGETSV_DEPTHSV_DEPTHGREATEREQUALSV_DEPTHLESSEQUALSV_COVERAGESV_INNERCOVERAGESV_STENCILREFUnknown creatorUnknown library functionMicrosoft (R) HLSL Shader Compiler 10.1$Invalidrootsig_1_0rootsig_1_1D3DCompile: Entry point must specify the RootSignature define name

[RootSignature(%s)]void ___DummyMainForRS(){}
ps_5_1___DummyMainForRSD3DCompile: Invalid flags specifiedD3DCompile: cannot specify source and binary debug namesD3DCompile: pEntrypoint pointer is invalid__fx_2_0__Shader@0x%pD3DCompile: Entry point cannot be specified for a library (mark library entry points with the export keyword)D3DCOMPILER_SAVE_REPLAYD3DCOMPILER_USE_REPLAY#pragma pack_matrix(row_major)
#pragma pack_matrix(column_major)
#pragma pack_matrix()
#pragma ruledisable "%s"
#line %u %.*s
#line %u
0x%x#pragma def (%s, %s, %g, %g, %g, %g)
#pragma warning (once:%d)
#pragma warning (disable:%d)
#pragma warning (error:%d)
D3DCompressedData(%u,%u-%u): (%u,%u): %s X%u: errorError creating error stringwarning treated as errorwarningUnable to create warning stringversion tokentoken '%s'integer '%u'integer '%dl'integer '%uul'integer '%I64d'integer '%I64uu64'float '%g'float '%gh'float '%gf'float '%gl'string constantend of lineend of filetokensyntax error : unexpected %s--- Compilation status for library function '%s' ---
comment continues past end of file1.#IND1.#INF1.#QNAN1.#SNANhex value truncated to 64 bitsoctal value truncated to 64 bitsdecimal value truncated to 64 bitsstring continues past end of filestring continues past end of linecharacter continues past end of filehalfsbyteshortushortlongulongTexture2DArrayMSSamplerComparisonStateStateBlockRasterizerDepthStencilBlendPointStreamLineStreamTriangleStreamInputPatchOutputPatchRWTexture1DRWTexture1DArrayRWTexture2DRWTexture2DArrayRWTexture3DRWBufferByteAddressBufferRWByteAddressBufferStructuredBufferRWStructuredBufferRWStructuredBuffer(Incrementable)RWStructuredBuffer(Decrementable)AppendStructuredBufferConsumeStructuredBufferConstantBufferTextureBufferRasterizerOrderedBufferRasterizerOrderedByteAddressBufferRasterizerOrderedStructuredBufferRasterizerOrderedTexture1DRasterizerOrderedTexture1DArrayRasterizerOrderedTexture2DRasterizerOrderedTexture2DArrayRasterizerOrderedTexture3Dclass.$super$super**<,%u>typedef precise column_major const unorm snorm array_index  %s%s#hlsl_full_pathhlsl_full_pathmalformed #hlsl_full_pathNo include handler specified, can't perform a #include. Use D3DX APIs or provide your own include handler.failed to open source file: '%s'C#unexpected tokens following preprocessor directiveunexpected end of file__FILE____LINE__DIRECT3DD3DXD3D10_COMPILERHLSL_VERSIOND3DX_VERSIONdefineelififdefifndefincludelinepragmaundefdefinedinvalid or unsupported integer constant expressioninternal error: stack underflowdivision by zero in preprocessor expressionStackinternal error: out of memorysyntax errorinvalid preprocessor command '%s'duplicate macro parameter '%s'#hlsl_full_path must be the first content in a source filetoo many nested #includeserror: %sunexpected #elifunexpected #elif following #elseunexpected #elseunexpected #else following #elseunexpected #endifpack_matrixruledisablemessagefeature'%s' : unknown pragma ignoredrow_majorcolumn_majoroncedisabledefault#pragma feature(%s) must appear before any local declarationunrecognized feature '%s' requested in '#pragma feature(...)''%s' : macro redefinitionfunctional defines in preprocessor expressions not yet implementedunexpected end of file in macro expansionArgnot enough actual parameters for macro '%s'#@##internal error: production failedLegacyLocalResourceArraysinvalidscopevariabletypefunctiontechniqueglobal variableslocal variablesannotation memberspassesmembersloop variablesstruct/class membersmethodsfunction parametersinitial valuevalueinitializerdefault value(unknown scope entry kind)(unknown scope value kind)namespaceHhH4TPPH80$memory exhausted	"#'$%*).78& !;<=> !1	

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Valueinternal error: this-relative %s '%s' found outsideof function scopestatic method %s cannot refer to instance membersundeclared identifier '%s'data member'%s': initializer does not match typeobject literals are not allowed inside functionsall global variables are implicitly constant when compiling a library.global variables are implicitly constant, enable compatibility mode to allow modificationglobal variables are implicitly constant, variables of classes with interface inheritance can never be modifiedl-value specifies const objectint or unsigned int type requiredscalar, vector, or matrix expectedoperator cannot be used with a bool lvaluecouldn't cast expression to integerunary negate of unsigned value is still unsignedcouldn't cast expression to boolean for logical not operatortype mismatchsigned/unsigned mismatch, unsigned assumedcouldn't cast expression to boolean for logical operatorcomma expression used where an initializer list may have been intendedcomma expression used where a vector constructor may have been intendedconstructors only defined for numeric base typescannot convert from 'object type' to 'numeric type'incorrect number of arguments to numeric-type constructorconditional must be numerictype mismatch between conditional valuesdimension of conditional does not match valuearray, matrix, vector, or indexable object type expected in index expressioninvalid type for index - index must be a scalar, or a vector with the correct number of dimensionsSub index listmipssampleLengthSwizzleinvalid subscript '%s'PartialsInputsOutputsout parameters require l-value arguments (given argument is implicitly const, such as a global)out parameters require l-value arguments'%s': %ss are limited to no more than %u parameters (%u given)'%s': no matching %u parameter %sPossible %ss are:    %sParametersMethod and Parametersintrinsic functionmethod%s does not have method '%s''%s': static methods cannot be called on objects%s object does not have methods%s object does not have method '%s'intrinsic methodvector dimension must be a literal scalar expressionvector dimension must be between 1 and %uvector element type must be a scalar typematrix dimensions must be literal scalar expressionsmatrix dimensions must be between 1 and %umatrix element type must be a scalar typeuntyped textures are deprecated in strict modethe 'sampler1D' keyword is deprecated in strict mode; use 'SamplerState' insteadthe 'sampler2D' keyword is deprecated in strict mode; use 'SamplerState' insteadthe 'sampler3D' keyword is deprecated in strict mode; use 'SamplerState' insteadthe 'samplerCUBE' keyword is deprecated in strict mode; use 'SamplerState' insteadthe 'stateblock' keyword is deprecated in strict modenon-numeric sample countsample count must be non-zeronon-numeric vertex countvertex count must be non-zeromatrix types cannot be both column_major and row_majornon-matrix types cannot be declared 'row_major' or 'column_major'%cnorm can not be used with typeunsigned can not be used with typeobject element type cannot be an object typeobject's templated type must have at least one elementelements of typed buffers and textures cannot be arrayselements of typed buffers and textures must fit in four 32-bit quantitiesclasses and interfaces are not supported in librariesinterfaces cannot inherit from other typesbase type is not a struct, class or interfacemultiple concrete base types specified'%s': class does not implement method %sarray dimensions of type must be explicitarray dimensions must be literal scalar expressionsarray dimension must be between 1 and 65536secondary array dimensions must be explicitinterface arrays cannot be multi-dimensionalredefinition of type with struct/classredefinition of type with interfaceAddUint64bAllMemoryBarrierAllMemoryBarrierWithGroupSyncCheckAccessFullyMappedstatusD3DCOLORtoUBYTE4DeviceMemoryBarrierDeviceMemoryBarrierWithGroupSyncEvaluateAttributeAtSampleindexEvaluateAttributeCentroidEvaluateAttributeSnappedoffsetGetRenderTargetSampleCountGetRenderTargetSamplePositionGroupMemoryBarrierGroupMemoryBarrierWithGroupSyncInterlockedAddresultoriginalInterlockedAndInterlockedCompareExchangecompareInterlockedCompareStoreInterlockedExchangeInterlockedMaxInterlockedMinInterlockedOrInterlockedXorNonUniformResourceIndexProcess2DQuadTessFactorsAvgRawEdgeFactorsInsideScaleRoundedEdgeFactorsRoundedInsideFactorsUnroundedInsideFactorsProcess2DQuadTessFactorsMaxProcess2DQuadTessFactorsMinProcessIsolineTessFactorsRawDetailFactorRawDensityFactorRoundedDetailFactorrRoundedDensityFactorProcessQuadTessFactorsAvgProcessQuadTessFactorsMaxProcessQuadTessFactorsMinProcessTriTessFactorsAvgRoundedInsideFactorUnroundedInsideFactorProcessTriTessFactorsMaxProcessTriTessFactorsMin__test_intrin1__test_intrin2__test_intrin3__test_intrin4abortacosallanyasdoubleasfloatasinasintasuintatanatan2ceilclampclipcoshcountbitscrossddxddx_coarseddx_fineddyddy_coarseddy_finedegreesdeterminantdistancedoterrorfFormat...exp2f16tof32f32tof16faceforwardNINgfirstbithighfirstbitlowfloorfmafmodfracfrexpfwidthisfiniteisinfisnanldexplengthlerphlog10log2modfipmsad4referenceaccumnoisenormalizeprintfradiansreflectnrefractrireversebitsroundrsqrtsaturatesignsinhsmoothstepsource_marksqrtsteptantanhtex1Dtex1Dbiastex1Dgradtex1Dlodtex1Dprojtex2Dtex2Dbiastex2Dgradtex2Dlodtex2Dprojtex3Dtex3Dbiastex3Dgradtex3Dlodtex3DprojtexCUBEtexCUBEbiastexCUBEgradtexCUBElodtexCUBEprojtransposeAppendRestartStripCalculateLevelOfDetailCalculateLevelOfDetailUnclampedGetDimensionswidthlevelsLoadSampleSampleBiasSampleCmpSampleCmpLevelZeroSampleGradSampleLevelelementsGatherGatherAlphao1o2o3o4GatherBlueGatherCmpGatherCmpAlphaGatherCmpBlueGatherCmpGreenGatherCmpRedGatherGreenGatherRedheightsamplesGetSamplePositiondepthbyteOffsetLoad2Load3Load4StoreStore2Store3Store4countstrideDecrementCounterIncrementCounterConsumedwordfloat4float4x4matrixpixelshadervectorvertexshader'%s': identifier represents a %s, not a variableinternal error: unable to process intrinsic'%s': identifier represents a %s, not a function'%s': ambiguous function callcentergloballycoherentsingleunrecognized identifier '%s''%s': too many target specifiers givenduplicate usages specifiedconstinterp usage cannot be used with linear, noperspective, or centroid usageconflicting geometry typesAttrParams$clip_outputsAttributesclipplanes'clipplanes' attribute is ignored in library functionslocation semantics do not apply to %sslocation semantics cannot be specified on memberspackoffset cannot have a target qualifiersampler requires an 's' or 't' registerbuffer requires a 't' registertexture requires a 't' or 's' registerUAV requires a 'u' registercbuffer requires a 'b' registertbuffer requires a 't' registerusage semantics do not apply to %ssbind semantics cannot be specified for this objectincorrect bind semanticduplicate usage semantic ignoredredefinition of '%s''%s': variable is declared as tbuffer, which is not supported for libraries yet'%s': invalid shader target/usage'%s': %s cannot be target specific'%s': %s cannot be declared 'inline''%s': %s cannot be declared 'single''%s': interfaces cannot contain data'%s': interfaces cannot be declared in buffers'%s': extern %s cannot be declared 'static''%s': uniform %s cannot be declared 'static''%s': extern %s cannot be declared 'groupshared''%s': uniform %s cannot be declared 'groupshared''%s': groupshared variables cannot hold resources'%s': types cannot contain members of their own type'%s': interfaces cannot be members'%s': %s cannot be declared 'const''%s': output parameters cannot be declared 'const''%s': %s cannot be void'%s': %s cannot be declared 'static''%s': %s cannot be declared 'uniform''%s': %s cannot be declared 'uniform out''%s': %s cannot be declared 'extern''%s': %s cannot be declared 'groupshared''%s': %s cannot be declared 'shared''%s': %s cannot be declared 'volatile''%s': only first dimension can be implicit'%s': array dimensions of %s must be explicit'%s': implicit array missing %s'%s': implicit array type does not match %s'%s': array dimension must be between 1 and 65536redefinition of formal parameter '%s''%s': static members can only be defined in global scopes'%s': static member not found in class'%s': member not a static variableD3D12 constant/texture buffer template element can only be a struct'%s': declaration type differs from definition typeConflicting register semantics: '%s' and '%s''%s': interfaces cannot have semantics'%s': %s cannot have semantics'%s': %s cannot have annotationsstream parameters can only be single-element types'%s': out parameters cannot have default valuespotentially unintended use of a comma expression in a variable initializer'%s': variables of type '%s' cannot be declared 'static''%s': variables containing textures, samplers and UAVs can only be declared 'static' if the variable only contains resources'%s': %s cannot have %ss'%s': non-numeric uniform %s cannot have %ss'%s': output only %s cannot have %ss'%s': %s must be a literal expressionstatic interfaces cannot have initializersInitializer used on a global 'const' variable. This requires setting an external constant. If a literal is desired, use 'static const' instead.'%s': missing %s'%s': incorrect array size'%s' used but not defined'%s': functions cannot be declared 'uniform''%s': functions cannot be declared 'extern''%s': interface methods cannot be static'%s': function return value cannot contain Effects objects'%s': method not found in class'%s': interface methods cannot be declared outside of an interface'%s': library functions cannot have a target'%s': functions cannot have a target'%s': library functions are supported only for PS and VS shaders'%s': void function cannot have a semantic'%s': missing default value for parameter '%s''%s': unsupported type qualifier for a library function parameter '%s''%s': library function parameters cannot have duplicate semantic '%s''%s': library function parameter and return cannot have duplicate semantic '%s''%s': doubles cannot be used as library function inputs or outputs. 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implicitly output parameter cannot %sconvert %sfrom '%s' to '%s''%s': cannot %sconvert %sfrom '%s' to '%s''%s': conversion from larger type to smaller, possible loss of dataconversion from larger type to smaller, possible loss of data'%s': implicit truncation of vector typeimplicit truncation of vector typeNMLKpackoffset is only allowed in a constant bufferregister offset must be a literal scalar expression'%s' matches a variable in the template shader but the type layout does not match'%s': place-holder template resources can only be simple resources, structs and arrays are not supportedunsigned integer literal %I64u too large, truncatedSetComputeShaderSetDomainShaderSetHullShaderSetGeometryShaderSetPixelShaderSetVertexShaderSetRasterizerStateSetBlendStateSetDepthStencilStateOMSetRenderTargetsConstructGSWithSOBindInterfacesD3D10_SHADER_DEBUGD3D10_SHADER_SKIP_OPTIMIZATIOND3D10_SHADER_PARTIAL_PRECISIOND3D10_SHADER_NO_PRESHADERD3D10_SHADER_AVOID_FLOW_CONTROLD3D10_SHADER_PREFER_FLOW_CONTROLD3D10_SHADER_ENABLE_BACKWARDS_COMPATIBILITYD3D10_SHADER_IEEE_STRICTNESSinvalid compiler flag %sparameter count mismatch (%s)this FX API is not available in this part your program (%s)Unrecognized FX function call (%s)StatesDX9-style 'LHS = ' syntax is deprecated in strict modeValues%u%sunsupported compiler target '%s'the debug info flag can only be set globally%s shader fragments are not supportedDX9-style 'compile' syntax is deprecated in strict modeDX9-style '= sampler_state' syntax is deprecated in strict mode'%s': void functions cannot return a value'%s': function must return a valuepotentially unintended use of a comma expression in a return statementif statement conditional expressions must evaluate to a scalarcould not cast condition to booleanscalar value expectedcould not cast condition to uintnon-scalar case expressionnon-numeric case expressionCaseStmts'%s': loop control variable conflicts with a previous declaration in the outer scope; most recent declaration will be usedinternal error: unable to add non-conflicting symbolStmtsspace is only supported for shader targets 5.1 and higher]-.g
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:cabinet.dllFCICreateFCIAddFileFCIFlushCabinetFCIDestroyFDICreateFDICopyFDIDestroyD0x%I64xcscs_4_0cs_4_1cs_5_1dsds_5_0ds_5_1fx_2_0gs_4_0gs_4_1gs_5_0gs_5_1hshs_5_0hs_5_1liblib_4_0lib_4_1lib_4_0_level_9_1lib_4_0_level_9_1_vs_onlylib_4_0_level_9_1_ps_onlylib_4_0_level_9_3lib_4_0_level_9_3_vs_onlylib_4_0_level_9_3_ps_onlylib_5_0psps.1.0ps.1.1ps.1.2ps.1.3ps.1.4ps.2.0ps.2.aps.2.bps.2.swps.2.xps.3.0ps.3.swps_1_0ps_1_1ps_1_2ps_1_3ps_1_4ps_2_0ps_2_aps_2_bps_2_swps_2_xps_3_0ps_3_swps_4_0_level_9_0txtx_1_0vsvs.1.0vs.1.1vs.2.0vs.2.avs.2.swvs.2.xvs.3.0vs.3.swvs_1_0vs_1_1vs_2_0vs_2_avs_2_swvs_2_xvs_3_0vs_3_swvs_4_0_level_9_0vs_5_1FLPLFLPLFLobreakpif_cbreak_coDoToCboolean constant register '%s' must be defined as a variable of type bool onlyinteger constant register '%s' must be defined as a variable of type int3 or int4 onlyConstant variable '%s' bound to register greater than 8191 (%d requested)Sampler variable '%s' does not specify the sampler type.  Explicit sampler types required for asm fragments.POSITIONBLENDWEIGHTBLENDINDICESNORMALPSIZETEXCOORDTANGENTBINORMALTESSFACTORPOSITIONTCOLORFOGVFACEVPOSDIFFUSESPECULARinvalid register, input, or constant name '%s'Invalid input register '%s' specifiedaddressing operations are not allowed on input registers '%s'Invalid pixel shader input register '%s' specifiedaddressing operations not allowed on temporary registers '%s'constant register '%s' must be defined as a variable '%s'constant register address out of bounds on constant '%s', size %d, offset %dInvalid output register '%s' specifiedaddressing operations are not allowed on output registers '%s''%s' is not a valid register name.  Registers must start with v_, r_, c_, b_, or i_ depending on the register type. (o_ for vs_3_0 only)shader version expectedvs_1_0 is no longer supported; using vs_1_1ps_1_0 is no longer supported; using ps_1_1unrecognized shader versiononly vs_1_1, vs_2_0, vs_2_x, vs_2_sw, ps_2_0, ps_2_x, and ps_2_sw are supported for assembly fragmentsentrypointasinstruction coissue is not supported in this shader versioninstruction predication is not supported in this shader versionscalar registers cannot be maskednot cannot be used with other modifiersnegate and divide modifiers cannot be combinedinvalid complement expressioncomplement is not supported in this shader versioncomplement cannot be used with other modifiersscalar registers cannot be swizzledonly one address register reference allowed in a relative address expression'%s' is not a valid instruction in this shader versioninvalid instruction modifiers '%s'x8x4x2d2d4d8volumeppblendweightblendindicesnormalpsizetangentbinormaltessfactorpositiontcolorfoggtlebiasbx2dzdbdwdatemporary, constant, and output registers are not allowed in vs_3_0 assembly fragmentstemporary and constant registers are not allowed in assembly fragmentsinvalid register '%s[%u]'invalid register '%s[...]'invalid register '%s'invalid mask '%s'invalid swizzle '%s'call, callnz, label, and ret instructions are not allowed in assembly fragmentsMatrices cannot be specified in temp registers with the fragment linkersource modifiers are not allowed on destination parametersrelative addressing of destination parameters is not supported in this shader versiononly one address register reference is allowed in a relative address expressionpredicates are not supported in this shader versionsource modifiers are not allowed on predicatesrelative addressing of predicates is not supported in this shader versionsource modifiers incompatible with SUB instructiononly a0.x is allowed as a relative address register in vs_1_1internal error: instruction size mismatchMicrosoft (R) D3DX9 Shader Assembler 10.1fragment info exceeds maximum comment sizedebug info exceeds maximum comment size; no debug info emitted !1234zw89&'!! !>?>GHWXYZTU"opqr\]!h\]{=abjBjw#z	

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MAXMIPLEVELMAXLODSRGBTEXTUREELEMENTINDEXDMAPOFFSETMAGFILTERFILTERMINFILTERMIPFILTERMIPMAPLODBIASMIPLODBIASD3DEffectCompilerEffects deprecated for D3DCompiler_47register or offset bind %s.%s not validregister or offset bind %s not validInternal Error - there was a problem getting a type sizeThere was an unexpected error in the parse treefloat1float2float3int1int2int3int4uint1uint2uint3uint4bool1bool2bool3bool4float1x1float1x2float1x3float1x4float2x1float2x2float2x3float2x4float3x1float3x2float3x3float3x4float4x1float4x2float4x3int1x1int1x2int1x3int1x4int2x1int2x2int2x3int2x4int3x1int3x2int3x3int3x4int4x1int4x2int4x3int4x4uint1x1uint1x2uint1x3uint1x4uint2x1uint2x2uint2x3uint2x4uint3x1uint3x2uint3x3uint3x4uint4x1uint4x2uint4x3uint4x4bool1x1bool1x2bool1x3bool1x4bool2x1bool2x2bool2x3bool2x4bool3x1bool3x2bool3x3bool3x4bool4x1bool4x2bool4x3bool4x4Variable has an invalid type; is the structure definition empty?%s does not support structs without membersinterfaces cannot be embedded in other typesIncorrect number of rows or columnsObjects not allowed in structuresOnly single-dimensional object arrays are allowedUnexpected template typeUnexpected component typeUnexpected node encountered when trying to determine typeThere was a problem getting annotationsOnly numeric types and strings are allowed as annotationsThis object can only be bound to one slot in this version of EffectsNumeric variables ('%s') can't be shared; share the containing cbuffer insteadOnly numeric variables ('%s') can be added to a cbufferError: constant buffer %s has both user-defined offset and compiler-assigned offsetsBuffers can only be bound to one slot in this version of EffectsConstant buffers, functions, and techniques cannot be nested inside of constant buffersUnnamed objects are not allowedRedefinition of pass "%s"PassSamplerDX9-style assignment syntax is deprecated in technique10 pass blocks in favor of new function call syntaxDeprecated DX9 state '%s' is being ignored for %sDeprecated DX9 state '%s' is being ignored for %s; use state '%s' insteadDX9 state '%s' is not supported in %s; use compatibility mode to ignoreDX9 state '%s' is not supported in %s; convert to '%s' or use compatibility mode to ignoreUnrecognized state '%s'State '%s' belongs in %s blocks, not %s blocksGenerateMips is not supported in %sState '%s' is not indexedMax index for effect state '%s' is %dIndex is required for state '%s'Internal error: unrecognized SB API Call%s is not supported on %sInternal error: unrecognized assignment type(unnamed)ERROR: Semantic %s is not supported in fx_4_1.Stage linkage warning: Semantic %s has been placed in different registers in the two stages.Stage linkage warning: Semantic %s has been inconsistently defined in the two stages.Stage linkage warning: Semantic %s is read from, but it's never written to.%s: ERROR: If either a HullShader or DomainShader is set then both must be set. Technique %s, Pass %s.%s: ERROR: No valid %s-%s combination could be found in Technique %s, Pass %s.%s: WARNING: There exist invalid %s-%s combinations in Technique %s, Pass %s, depending on which elements of the specified shader array(s) are chosen.'%s': samplers can only be used with declared textures or texture assignmentsAssignment %s: Reference to shader variable '%s' not valid for %s techniques because it uses an uninitialized shaderAssignment %s: Reference to shader variable '%s' not valid for %s techniques because it uses an unsupported shader modelAssignment %s: Reference to shader variable '%s' not valid for %s techniques because it is missing interface parameter bindingsUnrecognized RHS value in assignment: '%s'There was an error compiling HLSL shader variableUndefined shader variable '%s'%s can't operate on array referencesStream output geometry shaders can only be created from valid 4.0+ vertex and geometry shaders%s can only be used with non-NULL shadersInvalid shader type used with %sIdentifier invalid or not found (were you attempting a forward reference?)%s does not support multi-output stream outStreamOut declarations must be a literal stringInvalid StreamOut decl: %sInvalid StreamOut declStreamOut rasterization stream index must be a literal%s does not support interface bindingsinvalid interface binding parametercannot bind interfaces to classes in tbuffersBindInterfaces used with a shader that does not have interface parametersIncorrect number of parameters for BindInterfacesinterface variables can only be initialized with concrete classesIllegal initializer for a numeric variableCan't create/set an invalid shader. Make sure your shader is valid, and make sure you're not using asm shaders in SM4.0Illegal initializerUnrecognized token %sInternal error in compilerShader model %s is not allowed in D3D10 techniquesThere was an error compiling expressionAssignment %s: Non-array right-hand type expectedAssignment %s: Only literal right-hand side values are allowed in state blocks in Effects performance modeAssignment %s: Left-hand side type does not match right-hand side typeAssignment %s: Attempting to assign an incompatible inline shaderAssignment %s: Inline shader missing interface parameter bindingsAssignment %s: Only 0 and NULL are valid constants for an object assignmentAssignment %s: Dimensionality mismatch (LHS expects %d, RHS has %d)Invalid assignment index (%u). Maximum allowed is %u.TEXTURE assignments inside of samplers cannot be variable indexedTEXTURE assignments inside of samplers cannot be expression indexedAssignment %s: Expressions cannot be evaluated to produce objects, though they may be used to index into arrays of objectsAssignment %s: Objects left-hand sides cannot be assigned to expressionsEffect file is too large, try reducing the number of techniques or compiling without debug infoID3D10Effect::ParseSODecl - Invalid output slotID3D10Effect::ParseSODecl - Non-digit '%c' in output slotrgbaID3D10Effect::ParseSODecl - invalid mask declaration '%s'$SKIPFLATGOURAUDPHONGPOINTSRCCOLORINVSRCCOLORSRCALPHAINVSRCALPHADESTALPHAINVDESTALPHADESTCOLORINVDESTCOLORSRCALPHASATBOTHSRCALPHABOTHINVSRCALPHABLENDFACTORINVBLENDFACTORMIRRORONCECWCCWLESSEQUALNOTEQUALGREATEREQUALINCRSATDECRSATEXPEXP2LINEARUSEWMATERIALCOLOR1COLOR2VWCOORD0COORD1COORD2COORD3REDGREENBLUEALPHAQUADRATICCUBICQUINTICDISCRETECONTINUOUSDISABLE0WEIGHTS1WEIGHTS2WEIGHTS3WEIGHTSTWEENINGCLIPPLANE0CLIPPLANE1CLIPPLANE2CLIPPLANE3CLIPPLANE4CLIPPLANE5REVSUBTRACTPASSTHRUCAMERASPACENORMALCAMERASPACEPOSITIONCAMERASPACEREFLECTIONVECTORSPHEREMAPSELECTARG1SELECTARG2MODULATEMODULATE2XMODULATE4XADDSIGNEDADDSIGNED2XADDSMOOTHBLENDDIFFUSEALPHABLENDTEXTUREALPHABLENDFACTORALPHABLENDTEXTUREALPHAPMBLENDCURRENTALPHAPREMODULATEMODULATEALPHA_ADDCOLORMODULATECOLOR_ADDALPHAMODULATEINVALPHA_ADDCOLORMODULATEINVCOLOR_ADDALPHABUMPENVMAPBUMPENVMAPLUMINANCEDOTPRODUCT3MULTIPLYADDLERPSELECTMASKCURRENTTEXTURETFACTORTEMPCONSTANTCOMPLEMENTALPHAREPLICATEPYRAMIDALQUADGAUSSIANQUADCOUNT1COUNT2COUNT3COUNT4PROJECTEDSPOTDIRECTIONALXYZXYZRHWXYZB1XYZB2XYZB3XYZB4XYZB5XYZWLASTBETA_UBYTE4LASTBETA_D3DCOLORTEX0TEX1TEX2TEX3TEX4TEX5TEX6TEX7TEX8TEXCOORDSIZE1_0TEXCOORDSIZE1_1TEXCOORDSIZE1_2TEXCOORDSIZE1_3TEXCOORDSIZE1_4TEXCOORDSIZE1_5TEXCOORDSIZE1_6TEXCOORDSIZE1_7TEXCOORDSIZE2_0TEXCOORDSIZE2_1TEXCOORDSIZE2_2TEXCOORDSIZE2_3TEXCOORDSIZE2_4TEXCOORDSIZE2_5TEXCOORDSIZE2_6TEXCOORDSIZE2_7TEXCOORDSIZE3_0TEXCOORDSIZE3_1TEXCOORDSIZE3_2TEXCOORDSIZE3_3TEXCOORDSIZE3_4TEXCOORDSIZE3_5TEXCOORDSIZE3_6TEXCOORDSIZE3_7TEXCOORDSIZE4_0TEXCOORDSIZE4_1TEXCOORDSIZE4_2TEXCOORDSIZE4_3TEXCOORDSIZE4_4TEXCOORDSIZE4_5TEXCOORDSIZE4_6TEXCOORDSIZE4_7ZENABLEFILLMODESHADEMODEZWRITEENABLEALPHATESTENABLELASTPIXELSRCBLENDDESTBLENDCULLMODEZFUNCALPHAREFALPHAFUNCDITHERENABLEALPHABLENDENABLEFOGENABLESPECULARENABLEFOGCOLORFOGTABLEMODEFOGSTARTFOGENDFOGDENSITYRANGEFOGENABLESTENCILENABLESTENCILFAILSTENCILZFAILSTENCILPASSSTENCILFUNCSTENCILMASKSTENCILWRITEMASKTEXTUREFACTORWRAP0WRAP1WRAP2WRAP3WRAP4WRAP5WRAP6WRAP7WRAP8WRAP9WRAP10WRAP11WRAP12WRAP13WRAP14WRAP15CLIPPINGLIGHTINGAMBIENTFOGVERTEXMODECOLORVERTEXLOCALVIEWERNORMALIZENORMALSDIFFUSEMATERIALSOURCESPECULARMATERIALSOURCEAMBIENTMATERIALSOURCEEMISSIVEMATERIALSOURCEVERTEXBLENDCLIPPLANEENABLEPOINTSIZEPOINTSIZE_MINPOINTSIZE_MAXPOINTSPRITEENABLEPOINTSCALEENABLEPOINTSCALE_APOINTSCALE_BPOINTSCALE_CMULTISAMPLEANTIALIASMULTISAMPLEMASKPATCHEDGESTYLEDEBUGMONITORTOKENINDEXEDVERTEXBLENDENABLECOLORWRITEENABLETWEENFACTORBLENDOPPOSITIONDEGREENORMALDEGREESCISSORTESTENABLESLOPESCALEDEPTHBIASANTIALIASEDLINEENABLEMINTESSELLATIONLEVELMAXTESSELLATIONLEVELADAPTIVETESS_XADAPTIVETESS_YADAPTIVETESS_ZADAPTIVETESS_WENABLEADAPTIVETESSELLATIONTWOSIDEDSTENCILMODECCW_STENCILFAILCCW_STENCILZFAILCCW_STENCILPASSCCW_STENCILFUNCCOLORWRITEENABLE1COLORWRITEENABLE2COLORWRITEENABLE3SRGBWRITEENABLEDEPTHBIASSEPARATEALPHABLENDENABLESRCBLENDALPHADESTBLENDALPHABLENDOPALPHACOLOROPCOLORARG0COLORARG1COLORARG2ALPHAOPALPHAARG0ALPHAARG1ALPHAARG2RESULTARGBUMPENVMAT00BUMPENVMAT01BUMPENVMAT10BUMPENVMAT11TEXCOORDINDEXBUMPENVLSCALEBUMPENVLOFFSETTEXTURETRANSFORMFLAGSPATCHSEGMENTSFVFPROJECTIONTRANSFORMVIEWTRANSFORMWORLDTRANSFORMTEXTURETRANSFORMMATERIALDIFFUSEMATERIALAMBIENTMATERIALSPECULARMATERIALEMISSIVEMATERIALPOWERLIGHTTYPELIGHTDIFFUSELIGHTSPECULARLIGHTAMBIENTLIGHTPOSITIONLIGHTDIRECTIONLIGHTRANGELIGHTFALLOFFLIGHTATTENUATION0LIGHTATTENUATION1LIGHTATTENUATION2LIGHTTHETALIGHTPHILIGHTENABLEVERTEXSHADERPIXELSHADERVERTEXSHADERCONSTANTFVERTEXSHADERCONSTANTBVERTEXSHADERCONSTANTIVERTEXSHADERCONSTANTVERTEXSHADERCONSTANT1VERTEXSHADERCONSTANT2VERTEXSHADERCONSTANT3VERTEXSHADERCONSTANT4PIXELSHADERCONSTANTFPIXELSHADERCONSTANTBPIXELSHADERCONSTANTIPIXELSHADERCONSTANTPIXELSHADERCONSTANT1PIXELSHADERCONSTANT2PIXELSHADERCONSTANT3PIXELSHADERCONSTANT4ADDRESSUADDRESSVADDRESSWBORDERCOLORMAXANISOTROPYSAMPLERSTATEBLOCK$PRESHADER_VS$PRESHADER_PSID3DXEffectCompiler: Unexpected template typeID3DXEffectCompiler: Unexpected component typeID3DXEffectCompiler: Unexpected node encountered when trying to determine typeID3DXEffectCompiler: There was an error initializing parameter handlesID3DXEffectCompiler: There was an error initializing parameter annotation handlesID3DXEffectCompiler: There was an error initializing technique annotation handlesID3DXEffectCompiler: There was an error initializing pass annotation handlesID3DXEffectCompiler: There was an error initializing the compilerID3DXEffectCompiler: There was a problem getting variable typeID3DXEffectCompiler: Error initializing variable typeID3DXEffectCompiler: There was a problem in the parse treeID3DXEffectCompiler: There was a problem getting annotationsID3DXEffectCompiler: Only numeric types and strings are allowed as annotationsID3DXEffectCompiler: Error initializing annotation typeID3DXEffectCompiler: Only numeric types are allowed inside structuresID3DXEffectCompiler: Arrays must be either numeric, structure, string or shaderID3DXEffectCompiler: Only pass allowed within a techniqueID3DXEffectCompiler: Unrecognized state '%s'ID3DXEffectCompiler: State '%s' is not indexedID3DXEffectCompiler: Max index for effect state '%s' is %dID3DXEffectCompiler: Index is required for state '%s'ID3DXEffectCompiler: DMAPOFFSET sampler state can only be used with D3DDMAPSAMPLER (i.e. sampler index 256)ID3DXEffectCompiler: Invalid sampler index %dID3DXEffectCompiler: Invalid integer expression assignmentID3DXEffectCompiler: Unsupported sampler or stateblock expression (static usage not supported).ID3DXEffectCompiler: Can't set shader'ID3DXEffectCompiler: Geometry shader can only be set in fx_4_0 or higher.'ListID3DXEffectCompiler: Internal Error: Unexpected state.ID3DXEffectCompiler: Initializer list elements cannot be complex expressions or variablesID3DXEffectCompiler: Unexpected errorID3DXEffectCompiler: Error in type checkingID3DXEffectCompiler: State '%s' does not accept '%s' as a valueID3DXEffectCompiler: State '%s' accepts only dwords and idsID3DXEffectCompiler: FVFs must not evaluate to NULLID3DXEffectCompiler: Dword expressions for state '%s' must evaluate to NULLID3DXEffectCompiler: State '%s' was assigned an unsupported valueID3DXEffectCompiler: Error initializing assignment typeID3DXEffectCompiler: Internal error initializing assignment - missing type caseID3DXEffectCompiler: Assignment cannot be a structureID3DXEffectCompiler: Initializers must be numeric scalarsID3DXEffectCompiler: State '%s' cannot be assigned an array or structureID3DXEffectCompiler: State '%s' was not assigned a stateblock typeID3DXEffectCompiler: State '%s' was not assigned a sampler typeID3DXEffectCompiler: State '%s' was not assigned a texture typeID3DXEffectCompiler: State '%s' was assigned an incompatible typeID3DXEffectCompiler: State '%s' must be assigned a numeric scalar or a 4-float vectorID3DXEffectCompiler: State '%s' must be assigned a scalarID3DXEffectCompiler: State '%s' must be assigned a 3-vector or a 4-vector or a uint scalarID3DXEffectCompiler: State '%s' must be assigned a numeric valueID3DXEffectCompiler: Unexpected value type of state '%s' (internal error)ID3DXEffectCompiler::CompileEffect: There was an error compiling HLL shader parameterID3DXEffectCompiler::CompileEffect: Unrecognized value typeID3DXEffectCompiler::CompileEffect: Only 1-d shader arrays allowedID3DXEffectCompiler::CompileEffect: Shader arrays must be a previously defined parameterID3DXEffectCompiler::CompileEffect: Shader arrays index was not float or intID3DXEffectCompiler::CompileEffect: Shader arrays index %d out of bounds [0, %d]ID3DXEffectCompiler::CompileEffect: There was an error compiling expressionID3DXEffectCompiler::CompileEffect: Could not compile expression containing shader arrayID3DXEffectCompiler: There were no techniquesID3DXEffectCompiler: This sampler is used with a DX10-style texture intrinsic. This is not implemented in this version of the compiler.ID3DXEffectCompiler: Compilation failedOutput variable %s%s contains a system-interpreted value (%s) which must be written in every execution path of the shader.  Unconditional initialization may help. <| A%u (B%u)%s%s contains a system-interpreted value (%s) which should be written in every execution path of the shader <| A%u (B%u)emitting a system-interpreted value which is not written in every execution path of the shader. Unconditional initialization may help. <| A%u (B%u)emitting a system-interpreted value which may not be written in every execution path of the shader <| A%u (B%u)Inconsistent semantic definition: %s and %sDuplicate system value semantic definition: %s and %sDuplicate non-system value semantic definition: %s and %sReading uninitialized valuemaximum number of samplers exceeded. %s target can have a maximum of %u samplers%s target does not support texture lookupsThe maximum number of constant buffer slots is exceeded for a library (slot index=%u, max slots=%u)cbuffer register (b%u) used more than onceThe maximum number of sampler slots is exceeded for a library (slot index=%u, max slots=%u)sampler register (s%u) used more than onceThe maximum number of texture slots is exceeded for a library (slot index=%u, max slots=%u)texture register (t%u) used more than onceinternal error: output register missing semanticinternal error: input register missing semanticinternal error: emitting a denormNaN and infinity literals not allowed by shader modelmaximum number of inputs exceededoverlapping output semanticsinternal error: statistics append failed, byte count (%d) too large?internal error: non ordinal input/output foundmaximum cbuffer exceeded. target has %u slots, manual bind to slot %u failedcbuffer bank %u used more than oncemaximum cbuffer exceeded. target has %u slotsbooleanconstantiterator - Try reducing number of constant branches, take bools out of structs/arrays or move them to the start of the struct - Try reducing number of constants referenced - Try reducing number of loops, take loop counters out of structs/arrays or move them to the start of the struct - note that the target doesn't support texture sampling intrinsics - note that the target doesn't support textures - note that the target doesn't support UAVsmaximum %s %s register index (%u) exceeded - note that the minimum index is %u%smaximum %s %s register index (%u) exceeded%sinvalid register semantic '%s', or variable must be bound to multiple register banks (%c register binding required)%s registers live in the same name space as outputs, so they must be bound to at least %c%u, manual bind to slot %s failedmaximum %s register index exceeded, target has %d slots, manual bind to slot %s failedoverlapping register semantics not yet implemented '%c%u'Using sampler arrays with texture objects on DX9 targets is not yet implemented.Cannot use texture arrays on DX9 targets with multiple samplers.Invalid %s semantics - POSITIONT0invalid %s %s'%s', or '%s'one of '%s', '%s'Sample interpolation usage unsupported on %snointerpolation usage unsupported on %snoperspective usage unsupported on %sSV_SampleIndex isn't supported on %sMaximum semantic index (%d) exceeded: %d%s semantic '%s' cannot be centroid%s semantic '%s' has been deprecated; use '%s%d' insteadinvalid %s semantic '%s': Legal indices are in [%d,%d]invalid type used for '%s' %s semanticsintegralinvalid type used for '%s' %s semantics, must be %sinternal error: result violated port constraintsinternal error: non-vectorized pool violated port constraintsrelative address references too deepinternal error: multiple write to same outputalcannot match lerp because lerp factor is not _sat'dinternal error: instruction missing outputsinternal error: IF with size greater then 1 foundcannot clip from a swizzled vectorclip must be performed from a float3 vector for ps_1_x modelsclip must be performed from a float4 vector for ps_2_0 modelsinternal error: unexpected input register typeclip cannot be performed from a constant or literalconstant table info exceeds maximum comment size%s+%sc_%sb_%si_%ss_%smaximum temp register index exceededmaximum address register index exceededmaximum predicate register index exceededinternal error: unexpected output register typeinternal error: overlapping output writesmaximum input register index exceededmaximum constant register index exceeded - Try reducing number of constants referencedmaximum bool register index exceededmaximum sampler register index exceededmaximum loop register index exceededtarget does not support relative addressingtessfactor semantic out of orderconflicting quad/tri/isoline tessfactor semantictessfactor semantics must be in the same componentSV_Coverage and SV_InnerCoverage are mutually exclusive%s output limit (%d) exceeded, shader uses %d outputs.%s input limit (%d) exceeded, shader uses %d inputs.internal error: no semantic found on i/o argumentinternal error: output found with no semanticsemantic '%s' unsupported on %soutput %s%u used more than onceinteger inputs unsupported on %sNot all elements of SV_Position were written%s tessfactor %ss missingIndexable function parameters are unsupported (parameter: %u, "%s".Unsupported function parameter ("%s") type.Unsupported function parameter "%s" type.Clip planes cannot be addressed in %sClip planes must be non-literal constants with identity swizzles in %sUnsized MSAA textures aren't supported on this targetTextureCubeArray textures aren't supported on this targettexture2DMS cannot be more than %u samplesTexture1D types are unsupported on %sresource '%s' binding conflicts with template shaderresource '%s' binding not present in template shadertexture mismatch: texture used inconsistently, can only use one DX9-style texture intrinsic on individual samplers or sampler arrays$ElementRWStructuredBuffers may increment or decrement their counters, but not both.The array element count of GetDimensions on TextureCubeArray objects is unavailable on %scannot sample from non-floating point texture formats.sampler mismatch: sampler used inconsistently  l`UUe? 1?`UU??T@	@+7@T@	@7PTo@	@7o@"Tk@	u@7k@"To@	@7oP"Tk@	u@7kP"Pe@@
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00`OTHER`TEMP`PACKED<%s return value>hlslFlagshlslTargethlslEntryhlslDefinesinternal error: failed to write debug data to pdb streaminternal error: failed to add section contributioninternal warning: PDB Error string is "%S"internal error: failed to close debug infointernal error: failed to close PDBinternal error: failed to open PDB for writing in streaminternal error: failed to create debug info in PDBinternal error: failed to add code section to debug infointernal error: failed to add module to debug infointernal error: failed to create type info in PDBinternal error: failed to create inline type info in PDBinternal error: failed to create source file store in PDBinternal error: failed to close source file store in PDBinternal error: failed to close module in debug infointernal error: failed to commit type info in PDBinternal error: failed to commit inline type info in PDBinternal error: failed to add section header to debug infointernal error: failed to append section header to pdbinternal error: failed to close section header in debug infointernal error: failed to close debug info in PDBinternal error: failed to commit PDBinternal error: PDB data too largeinternal error: PDB stream truncatedinternal error: failed to close source file storeinternal error: failed to close type infointernal error: pdb append failedfxl_4_0too many arguments to target TXtoo many outputs to target TXclip not supported in texture shadersinvalid reference to input semantic '%s%d'invalid reference to output semantic '%s%d'0123456789abcdef.pdbVPosSV_ViewportArrayIndexColorFailed to log error, redirecting to debug output:
hs_5_0 patch constanths_5_0 control pointShader uses too many (%u) indexable literal values, the maximum allowed is %u, consider using less constant arraysSRVBy default, unbounded size descriptor tables are disabled to support frame captures in graphics tools. Use of unbounded (or large) size descriptor tables can produce unusually large and potentially unusable frame captures in graphics tools.  Please specify a reasonably small upper bound on table size.  If that isn?t an option, unbounded size descriptor tables can be enabled using the compiler using switch: /enable_unbounded_descriptor_tablesOverflow of resource binding range
%s binding ranges overlap for range %s[%d:%d]
Sum of temp registers and indexable temp registers exceeds limit of %u
sum of temp registers and indexable temp registers times %u threads exceeds the recommended total %u.  Performance may be reducedThe total amount of group shared memory (%u bytes) exceeds the %s limit of %d bytes
The maximum number of UAV slots is exceeded for a library (slot index=%u, max slots=%u)UAV register (u%u) used more than onceDebug instructions are unsupported in shader librariesinternal error gathering debug file informationMaximum %s control point count (%u) exceeded (%u).internal error: debug info append failed, byte count (%d) too large?internal error: RootSignature append failed, byte count (%d) too large?unknown errorRootSignature verification failed: %sRootSignature creation failed: %sinternal error: scalar instruction with too many inputsinternal error: expected binary instruction for scalar RHSmaximum number of interface pointers exceeded (%s max is %u)interface calls cannot be indexed with varying values%s can only emit to streams 0-%u%s can only emit to 1 stream%s does not support stream outwhen multiple GS output streams are used they must be pointlistsShaders compiled for %s can only have a single group shared data item
Group shared data for %s must have a count of elements (%u) equal to the number of threads in the thread group (%u)
Group shared data for %s must have an element size (%u) of at most %u bytes when compiling for %u theads
Group shared data for %s must be an array of elements
internal error: modifier used on addressinternal error: constant buffer used as addressinternal error: binary instruction expectedinternal error: vectorized instruction too largeinternal error: expected scalar RHS for instruction%s does not support structured buffersstructured buffer element size must be a multiple of %u bytes in %s (actual size %u bytes)structured buffer elements cannot be larger than %u bytes in %s (actual size %u bytes)offset texture instructions must take offset which can resolve to integer literal in the range -8 to 7MSAA Sample Index must be in the range 0 to %uMSAA Sample Index must be a literalSample Bias value is limited to the range [-16.00, 15.99], using %f instead of %freading uninitialized value%s does not support UAVs%s does not support Append/Consume buffersRasterizerOrdered objects are only allowed in 5.0+ pixel shaders%s does not support typed UAVsidiv currently not supported (instruction deprecated). For now, try using unsigned int types for div insteadtyped UAV stores must write all declared components.stores to group shared memory for %s targets must be indexed by an SV_GroupIndex only%s snap offset must be in the range -8 to 7cannot map expression to %s instruction setinternal error: failed to emit instructionSV_Position cannot be constinterpSV_Coverage input not supported on %sSV_Coverage not supported on %sSV_InnerCoverage input not supported on %sinvalid semantic '%s' on pixel shader output@DHLT\dpp`P@T0 0pBlendWeightBlendIndicesNormalPSizeTexcoordTangentBinormalPositionTFogDepthDiffuseSpecularTessfactorPsizeinternal error: no profile exists for this shader versionPSIZE must be a scalarvertex shader must minimally write all four components of POSITIONDEPTH must be a scalarpixel shader must minimally write all four components of COLOR0COLOR%d must be a four-component vectorCOLOR outputs must be contiguous from COLOR0 to COLORncannot map expression to vertex shader instruction setcannot map expression to pixel shader instruction setUnsupported texture type for %sinternal error: unexpected Alias on texture declarationrelative addressing not supported in vs_1_0 instruction setfxl_2_0internal error: gradient instruction sent to preshaderinternal error: no profile exists for this pixel shader versionSV_Target0COLOR0pixel shader must minimally write all four components of %s%s%d must be a four-component vectorSV_Target outputs must be contiguous from SV_Target0 to SV_TargetNrelative addressing not allowed for pixel shaderstexlod not supported on this targetShader model %s doesn't allow reading from position semantics.Invalid %s input semantic '%s'.sample interpolation usage unsupported on %sExceeded maximum number or index of output registers. Max allowed for this target is %d.internal error: invalid swizzle foundSV_Colorinternal error: no profile exists for this vertex shader versionFOG must be a scalarvertex shader must minimally write all four components of SV_Positioninternal error: DST test failureinternal error: no storage type for block outputinternal error: expression expectedexpressions returning objects in an array or struct not yet implementedcompile expression does not refer to a compilable function.  API calls such as ConstructGSWithSO and BindInterfaces can not be used in arguments to CompileShadercompile expression must specify a valid shader modelasm blocks have not yet been implementednon-trivial object expressions not yet implementedLibrary entry points cannot be overloaded ('%s')'%s': entrypoint not founda library must have at least one exported functionoverloaded function not foundinternal error: blob mismatch between level9 and d3d10 shaderinternal error: blob size mismatch between level9 and d3d10 shaderinternal error: blob content mismatch between level9 and d3d10 shaderSoftware\Microsoft\Direct3D\Direct3D12ForceShaderSkipOptimizationForceDebuggableD3DCOMPILER_FORCE_PREFER_FLOWFlags parameter is invalidFlags specified both compatibility and strict mode. These are mutually exclusiveFlag specified was exclusively a parse flag and not a compile flagppShader pointer is invalidunrecognized compiler target '%s'Only 3_x and earlier targets are supported on this compiler.Only 4_x targets supported on this compiler.ps_1_x is no longer supported; using ps_2_0ps_1_x is no longer supported; use /Gec in fxc to automatically upgrade to ps_2_0Alternately, fxc's /LD option allows use of the old compiler DLL
partial precision is not supported for target %s. Min-precision types may offer similar functionality.D3DCompile: resources_may_alias option is only valid for cs_5_0+ targetsD3DCompile: backwards compatibility mode (/Gec) option is not supported for SM5_1+ targetsD3DCompile: Gfa option cannot be used in SM_5_1+ unless all_resources_bound flag is specifiedFailed compiling 10_level_9 VS version of the library function '%s'.Failed compiling 10_level_9 PS version of the library function '%s'.out of memory during compilationinternal error: compilation aborted unexpectedlycpcinstanceidu%u'%s': variable declared but not defined%s does not support groupshared, groupshared ignored'%s': global variables cannot use the 'half' type in %s. To treat this variable as a float, use the backwards compatibility flag.'%s': %s does not support doubles as a storage type'%s': %s does not support 8-bit or 16-bit integers'%s': %s does not support 64-bit integers%s does not support 16-bit uint minimum-precision data'%s': %s does not support minimum-precision datainvalid packoffset location '%s'groupshared variables cannot contain resources such as textures, samplers or UAVscannot mix packoffset elements with nonpackoffset elements in a cbufferstream object '%s' cannot be declared in the global scopebranchn/aflattenforcecasefastoptunrolla uint specifying the number of iterations to unrollallow_uav_conditioninternal error: unrecognized statementTexture sample will be considered dependent since texcoord was not declared as at least float%dDX9-style intrinsics are disabled when not in dx9 compatibility mode.expressions with side effects are illegal as attribute parametersnon-literal parameter(s) found for attribute %scannot match attribute %s, non-uint parameters foundattribute %s expects the %s parameter to be a %s'%s(%s)' attribute expected, where '%s' is %s'%s(%s)' attribute expected, where '%s' are %sexpected %s parameter to be %s, got '%s'cannot match attribute %s, parameter %i is expected to be of type %s%ccan't match attribute %s, %d or 0 parameters expected, found %dcan't match attribute %s, %d parameter(s) expected, found %d, %sRootSignatureunknown attribute %s, or attribute invalid for this statementunknown attribute %s, or attribute invalid for this statement, valid attributes are: %sduplicate attribute %sCannot use %s attribute without specifying a 4-component SV_Position outputdoubles cannot be used as shader inputs or outputs. If you need to pass a double between shader stages you must pass it as two uints and use asuint and asdouble to convert between formsstream parameter must come from a literal expressionstructure being emitted has elements with no semantic defined%s does not support synchronization operations%s does not support thread synchronization operationssigned/unsigned mismatch between destination and value, unsigned assumed%s does not support interlocked operationsinterlocked targets must be groupshared or UAV elements%s only supports interlocked operations on scalar int or uint data%s does not support pull-model attribute evaluationattribute evaluation can only be done on values taken directly from inputs%s does not support pull-model evaluation of position'%s': undefined variableinvalid variable reference in static variable initializer.  Locals cannot be used to initialize static variablesinternal error: invalid access of unbound variableinternal error: unrecognized valueout of memoryall template type components must have the same typeunexpected error in GetTypeArgFlagsinvalid register specification, expected 'b' bindinginvalid register specification, expected 'b' or 'c' bindinginvalid register specification, expected 't' bindingUser defined %s buffer slots cannot be target specificBuffers may only be bound to one slot.Buffers may only be bound to one constant offset.Cannot declare streams as an input for geometry shader primitives, it must be its own parameter.SV_PrimitiveId is an invalid input semantic for geometry shader primitives, it must be its own parameter.SV_GSInstanceID is an invalid input semantic for geometry shader primitives, it must be its own parameter.for better compilation results, consider re-enabling rule "%s"for better compilation results, consider re-enabling rule 0x%08x'#pragma def' is no longer supported on DX10+ and 10level9 targets.  Use compatibility mode to allow compilation for now.error location reached from this locationwarning location reached from this location, forcing loop to unrollALLOW_INPUT_ASSEMBLER_INPUT_LAYOUTALLOW_STREAM_OUTPUTaddressUaddressVaddressWborderColorCBVcomparisonFuncCOMPARISON_NEVERCOMPARISON_LESSCOMPARISON_EQUALCOMPARISON_LESS_EQUALCOMPARISON_GREATERCOMPARISON_NOT_EQUALCOMPARISON_GREATER_EQUALCOMPARISON_ALWAYSDescriptorTableDESCRIPTOR_RANGE_OFFSET_APPENDDENY_VERTEX_SHADER_ROOT_ACCESSDENY_HULL_SHADER_ROOT_ACCESSDENY_DOMAIN_SHADER_ROOT_ACCESSDENY_GEOMETRY_SHADER_ROOT_ACCESSDENY_PIXEL_SHADER_ROOT_ACCESSDESCRIPTORS_VOLATILEDESCRIPTORS_STATIC_KEEPING_BUFFER_BOUNDS_CHECKSDATA_VOLATILEDATA_STATICDATA_STATIC_WHILE_SET_AT_EXECUTEflagsfilterFILTER_MIN_MAG_MIP_POINTFILTER_MIN_MAG_POINT_MIP_LINEARFILTER_MIN_POINT_MAG_LINEAR_MIP_POINTFILTER_MIN_POINT_MAG_MIP_LINEARFILTER_MIN_LINEAR_MAG_MIP_POINTFILTER_MIN_LINEAR_MAG_POINT_MIP_LINEARFILTER_MIN_MAG_LINEAR_MIP_POINTFILTER_MIN_MAG_MIP_LINEARFILTER_ANISOTROPICFILTER_COMPARISON_MIN_MAG_MIP_POINTFILTER_COMPARISON_MIN_MAG_POINT_MIP_LINEARFILTER_COMPARISON_MIN_POINT_MAG_LINEAR_MIP_POINTFILTER_COMPARISON_MIN_POINT_MAG_MIP_LINEARFILTER_COMPARISON_MIN_LINEAR_MAG_MIP_POINTFILTER_COMPARISON_MIN_LINEAR_MAG_POINT_MIP_LINEARFILTER_COMPARISON_MIN_MAG_LINEAR_MIP_POINTFILTER_COMPARISON_MIN_MAG_MIP_LINEARFILTER_COMPARISON_ANISOTROPICFILTER_MINIMUM_MIN_MAG_MIP_POINTFILTER_MINIMUM_MIN_MAG_POINT_MIP_LINEARFILTER_MINIMUM_MIN_POINT_MAG_LINEAR_MIP_POINTFILTER_MINIMUM_MIN_POINT_MAG_MIP_LINEARFILTER_MINIMUM_MIN_LINEAR_MAG_MIP_POINTFILTER_MINIMUM_MIN_LINEAR_MAG_POINT_MIP_LINEARFILTER_MINIMUM_MIN_MAG_LINEAR_MIP_POINTFILTER_MINIMUM_MIN_MAG_MIP_LINEARFILTER_MINIMUM_ANISOTROPICFILTER_MAXIMUM_MIN_MAG_MIP_POINTFILTER_MAXIMUM_MIN_MAG_POINT_MIP_LINEARFILTER_MAXIMUM_MIN_POINT_MAG_LINEAR_MIP_POINTFILTER_MAXIMUM_MIN_POINT_MAG_MIP_LINEARFILTER_MAXIMUM_MIN_LINEAR_MAG_MIP_POINTFILTER_MAXIMUM_MIN_LINEAR_MAG_POINT_MIP_LINEARFILTER_MAXIMUM_MIN_MAG_LINEAR_MIP_POINTFILTER_MAXIMUM_MIN_MAG_MIP_LINEARFILTER_MAXIMUM_ANISOTROPICmaxAnisotropymipLODBiasminLODmaxLODnumDescriptorsnum32BitConstantsRootFlagsRootConstantsStaticSamplerSHADER_VISIBILITY_ALLSHADER_VISIBILITY_VERTEXSHADER_VISIBILITY_HULLSHADER_VISIBILITY_DOMAINSHADER_VISIBILITY_GEOMETRYSHADER_VISIBILITY_PIXELSTATIC_BORDER_COLOR_TRANSPARENT_BLACKSTATIC_BORDER_COLOR_OPAQUE_BLACKSTATIC_BORDER_COLOR_OPAQUE_WHITETEXTURE_ADDRESS_WRAPTEXTURE_ADDRESS_MIRRORTEXTURE_ADDRESS_CLAMPTEXTURE_ADDRESS_BORDERTEXTURE_ADDRESS_MIRROR_ONCEvisibilityUnexpected token '%s'RootFlags cannot be specified more than onceUnexpected token '%s' when parsing root signatureExpected ',', found: '%s'Root signature flag values can only be 0 or flag enum values, found: '%s'Expected a root signature flag value, found: '%s'cbuffer register b#num32BitConstants must be defined for each RootConstantsConstant buffer register b# must be defined for each RootConstantsshader registershader register must be defined for each CBV/SRV/UAVExpected a register token (CBV, SRV, UAV, Sampler), found: '%s'Incorrect register type '%s' in CBV (expected b#)Incorrect register type '%s' in SRV (expected t#)Incorrect register type '%s' in UAV (expected u#)Incorrect register type '%s' in Sampler/StaticSampler (expected s#)Root descriptor flags cannot be specified for root_sig_1_0Root descriptor flag values can only be 0 or flag enum values, found: '%s'Expected a root descriptor flag value, found: '%s'Descriptor range flags cannot be specified for root_sig_1_0Descriptor range flag values can only be 0 or flag enum values, found: '%s'Expected a descriptor range flag value, found: '%s'Unexpected visibility value: '%s'.sampler register s#Sampler register s# must be defined for each static samplerUnexpected filter value: '%s'.Unexpected texture address mode value: '%s'.Parameter '%s' can be specified only oncemaxvertexcountthe maximum number of vertices emitted by this shaderMaxVertexCountinstancethe number of instances of this shader to execute simultaneouslynumthreadsX,Y,Zthe dimensions of the thread grouppatchconstantfuncfunction namethe name of the patch constant value evaluation functiondomaindomain typeone of "tri", "quad", or "isoline"partitioningpartitioning modeone of "integer", "pow2", "fractional_even", or "fractional_odd"outputtopologytopology typeone of "point", "line", "triangle_cw", or "triangle_ccw"outputcontrolpointsthe number of control points to emitmaxtessfactorlimitthe maximum tessellation factor to allowearlydepthstencilc1, c2, c3, c4, c5, c6the clip planes (up to 6) to useroot signatureisolinequadtrifractional_evenfractional_oddintegerpow2triangle_ccwtriangle_cw'%s': input parameter '%s' missing semantics, expected %s'%s': stream input parameter '%s' must be an inout parameter'%s': stream input parameter '%s' can only be used in geometry shaders'%s': input parameter '%s' cannot have a geometry specifier'%s': interface input parameters not yet implemented for hull shaders, use a global interface instead$%s'%s': input parameter '%s' conflicts with geometry specifier of previous input parameters'%s': may only have one InputPatch parameter'%s': Patch constant function must use the same input control point type declared in the control point phase.'%s': may only have one OutputPatch parameter'%s': Patch constant function must use the same output control point type returned from the control point phase.'%s': Patch constant function's output patch input should have %d elements, but has %d.'%s': stream input parameter '%s' must be an inout parameter '%s': InputPatch inputs can only be used in hull and geometry (5_0+) shaders'%s': OutputPatch inputs can only be used in the domain shaders and a hull shader's patch constant function'%s': input parameter '%s' must have a geometry specifier'%s': input parameter '%s' missing semantics'%s': input parameter '%s' patch size must be in the range [1,32]'%s': no input primitive specified, if your shader doesn't require inputs, then define an empty struct and give it the proper primitive type.internal error: unrecognized geometry shader input primitive type'%s': interfaces can only be inputs'%s': %s only allows one depth output'%s': function return value missing semantics'%s': output parameter '%s' missing semantics'%s': output parameters not yet implemented for control point shaders'%s': Compute shaders can't return values, outputs must be written in writable resources (UAVs).'%s': stream output parameter '%s' must be an inout parameter '%s': stream output parameter '%s' can only be used in geometry shaders'%s': Geometry shaders can't return values, outputs must be written to streams.'%s': Top-level return value is not completely initialized'%s': output parameter '%s' not completely initialized'%s': Top-level output parameter '%s' not completely initialized'%s': top-level interface arguments cannot be 'out''%s': %s semantic has no special meaning on 10level9 targets'%s' must have a max vertex count'%s' must have a max vertex count greater then 0%s does not allow instancingGS instance count must be at least 1%s only allows up to %u instancesthe product of the arguments of %s(%u,%u,%u) must be at least %uthe product of the arguments of %s(%u,%u,%u) must be less than or equal to %uthe final dimension specified (%u) for %s must be less than or equal to %u'%s': line output topologies are only available with isoline domains'%s': triangle output topologies are not available with isoline domains'%s' max tesselation factor must be in the range [1,64]Clip plane attribute parameters must be non-literal constantsIndexed expressions are illegal as attribute parametersRootSignature is allowed only for 5.0+ targetsRootSignature is not allowed in HS patch constant functionRootSignature attribute parameter must be a string'%s': recursive functions not allowed in %s'%s': When defining a pass-through control-point shader,you must declare an InputPatch object.'%s': When defining a pass-through control-point shader, the number of output control points must be zero or must match the input patch size.'%s': Not all control paths return a valueinternal error: unassociated return'%s': global structs and classes cannot be changedabstract interfaces not supported on %sinternal error: result register invalid%s does not support doubles%s does not support 8-bit or 16-bit integers%s does not support minimum-precision datacannot use casts on l-valuescannot cast the LHS of an assignment to an indexable object, consider using asuint, asfloat, or asdouble on the RHSin %s uints can only be used with known-positive values, use int if possibleinternal error: l-value expectedinternal error: inconsistent addressinginternal error: addressing inconsistent poolinternal error: inconsistent derivative writerinternal error: invalid sequence/cast expressionBitwise operations not supported on target %s.both sides of the && operator are always evaluated, side effect on '%s' will not be conditionalinternal error: AND operator inputs not boolboth sides of the || operator are always evaluated, side effect on '%s' will not be conditionalinternal error: OR operater inputs not bool%s emulates A / B with A * reciprocal(B). If the reciprocal of B is not representable in your min-precision type the result may not be mathematically correct..mips can only be used in a two-element indexing expression such as .mips[mip][element].sample can only be used in a two-element indexing expression such as .sample[sample][element]both sides of the ?: operator are always evaluated, side effect on '%s' will not be conditionalinternal error: unrecognized expressionDerivatives of indexed variables are not yet implemented.Output value '%s' is not completely initializednegatemultiplydividemodulo>===!=<<>>internal error: chain register invalid%s does not support double-precision floating-pointsigned integer division is not supported on minimum-precision types. Cast to int to use 32-bit division.integer divides may be much slower, try using uints if possible.signed integer remainder is not supported on minimum-precision types. Cast to int to use 32-bit division.integer modulus may be much slower, try using uints if possible.this operation cannot be used directly on resources containing doubles.internal error: argument missing context <| A%u (B%u)internal error: operand type mismatch%s cannot be used with doubles, cast to float first%s not supported on the given typeprotoscrobjtbitsisisciutiubiusicbuftbufpdr_tpdr_tbpdr_tspdr_spdr_scpdr_mpdr_?pdr_robjpdr_utpdr_ubpdr_usinput types for geometry shader must be arraysarray dimension for %s must be %iGS InputPatch semantics must live in the enclosed type, outer semantic ignored.register %s not valid%c%utexturesUAVs%s does not allow textures or samplers to be members of compound types%s does not allow writable textures, samplers or UAVs to be members of compound types with interface inheritancesemantics in type overridden by variable/function or enclosing typeresources such as textures, samplers or UAVs cannot contain other resourcesinternal error: unknown nodeSV_ClipDistance semantics cannot be used when using the clipplanes attributeSV_InstanceID semantic cannot be used with 10Level9 targetsDuplicated input semantics can't change type, size, or layout ('%s').globallycoherent can only be used with Unordered Access View buffersgloballycoherent cannot be used with append/consume buffers @  	  	(%s does not support indexing resourcestyped UAV loads are only allowed for single-component 32-bit element typesInterface-reachable members containing UAVs or group shared variables are not yet implementedrace condition writing to shared resource detected, note that threads will be writing the same value, but performance may be diminished due to contention.race condition writing to shared memory detected, note that threads will be writing the same value, but performance may be diminished due to contention.race condition writing to shared resource detected, consider making this write conditional.race condition writing to shared memory detected, consider making this write conditional.inner array index within group shared element must be a literal expression for %sarray reference cannot be used as an l-value; not natively addressableindex for an array of complex types containing doubles must be a literal expression%s array index must be a literal expressionResource being indexed is uninitialized.Resources being indexed cannot come from conditional expressions, they must come from literal expressions.element type of texture too large. Cannot exceed 4 componentsIncrementCounter/DecrementCounter are only valid on RWStructuredBuffer objectsAppend/Consume not compatible with buffer typecase ordinal too large for floating point representationcan't flatten with flow control when variable is bound to b registercan't use flow control on this profilecan't emit if statement with both gradients and program flow controlcan't flatten if statements that contain side effectsif statement was flattened due to nesting limits but it contains side effects and can't be flattenedinternal error: flattened side effectcan't flatten if statements that contain out of bounds array accessescan't force branch with gradients on non-inputscan't use branch and flatten attributes togethernon-empty case statements must have break or returnerror, duplicate default in switch statementerror, duplicate case %ucan't use branch, flatten, call  or case attributes togetherToo many nested flow control constructsFall-throughs in switch statements are not allowed.can't use call or forcecase attributes on switches in %s programsflow control depth too deep to honor call or forcecase attributecan't use loop and unroll attributes togethercan't use fastopt and unroll attributes togethercan't unroll loops marked with loop attributeliteral loop terminated early due to out of bounds array accessloop only executes for %d iteration(s), consider removing [loop]loop only executes for %d iteration(s), forcing loop to unrollcannot map loop to shader target, target does not support breakscan't use gradient instructions in loops with breakloop executes for more than %d iterations (maximum for this shader target), forcing loop to unrollloop doesn't seem to do anything, consider removing [loop]loop doesn't seem to do anything, forcing loop to unrollinfinite loop detected - loop writes no valuesloop will not exit early, try to make sure the loop condition as tight as possiblegradient instruction used in a loop with varying iteration, attempting to unroll the loopgradient instruction used in a loop with varying iteration; partial derivatives may have undefined valuetexture access must have literal offset and multisample indexloop simulation finished early, use /O1 or above for potentially better codegencannot unroll loop with an out-of-bounds array reference in the conditionforced to unroll loop, but unrolling failed.unable to unroll loop, loop does not appear to terminate in a timely manner (%d iterations)unable to unroll loop, loop does not appear to terminate in a timely manner (%d iterations) or unrolled loop is too large, use the [unroll(n)] attribute to force an exact higher numberbreak must be inside loopcontinue must be inside loopcontinue cannot be used in a switch%s does not support aborts%s does not support messagesabs on unsigned values is not meaningful, ignoringfma can only be used with double argumentsvalue cannot be infinity, isfinite() may not be necessary.  /Gis may force isfinite() to be performedvalue cannot be infinity, isinf() may not be necessary.  /Gis may force isinf() to be performedvalue cannot be NaN, isnan() may not be necessary.  /Gis may force isnan() to be performed%s is only valid in hull shadersasfloat can only be used on floating point values on %sasfloat cannot be used on min precision valuesasint cannot be used on %sasint cannot be used on min precision valuesasuint cannot be used on %sasuint cannot be used on min precision valuesasdouble can only be used on uint values on %sasuint can only be used on double values on %ssource_mark is most useful in /Od builds.  Without /Od source_mark can be moved around in the final shader by optimizations.Sampler parameter must come from a literal expression.tex1D will be considered dependent since texcoord was not declared as at least float2CheckAccessFullyMapped requires shader model 5 or higherAddUint64 requires shader model 5 or higherAddUint64 can only be applied to uint2 and uint4 operands'NonUniformResourceIndex' requires shader model 5 or higherintrinsic function '%s' is not yet implementedreturn type of texture too large. Cannot exceed 4 componentsclip can only be used with 1 to 4 components in %spow(f, e) will not work for negative f, use abs(f) or conditionally handle negative values if you expect them%s does not support 16-bit float conversionsTexture1D Load method for tiled resources requires shader model 5 or higherTexture1D Sample method for tiled resources requires shader model 5 or higherTexture1D SampleCmp method for tiled resources requires shader model 5 or higherTexture1D SampleCmpLevelZero method for tiled resources requires shader model 5 or higherTexture1D SampleLevel method for tiled resources requires shader model 5 or higherTexture1D SampleBias method for tiled resources requires shader model 5 or higherTexture2D Load method for tiled resources requires shader model 5 or higherTexture2D Sample method for tiled resources requires shader model 5 or higherTexture2D SampleCmp method for tiled resources requires shader model 5 or higherTexture2D SampleCmpLevelZero method for tiled resources requires shader model 5 or higherTexture2D SampleLevel method for tiled resources requires shader model 5 or higherTexture2D SampleBias method for tiled resources requires shader model 5 or higherTexture2D GatherRed method for tiled resources requires shader model 5 or higherTexture2D GatherGreen method for tiled resources requires shader model 5 or higherTexture2D GatherBlue method for tiled resources requires shader model 5 or higherTexture2D GatherAlpha method for tiled resources requires shader model 5 or higherTexture2D GatherCmpRed method for tiled resources requires shader model 5 or higherTexture2D GatherCmpGreen method for tiled resources requires shader model 5 or higherTexture2D GatherCmpBlue method for tiled resources requires shader model 5 or higherTexture2D GatherCmpAlpha method for tiled resources requires shader model 5 or higherTexture3D Sampler method for tiled resources requires shader model 5 or higherTexture3D SamplerBias method for tiled resources requires shader model 5 or higherTexture3D SamplerLevel method for tiled resources requires shader model 5 or higherTextureCube Sample method for tiled resources requires shader model 5 or higherTextureCube SampleCmp method for tiled resources requires shader model 5 or higherTextureCube SampleCmpLevelZero method for tiled resources requires shader model 5 or higherTextureCube SampleLevel method for tiled resources requires shader model 5 or higherTextureCube SampleBias method for tiled resources requires shader model 5 or higherTextureCube GatherRed method for tiled resources requires shader model 5 or higherTextureCube GatherGreen method for tiled resources requires shader model 5 or higherTextureCube GatherBlue method for tiled resources requires shader model 5 or higherTextureCube GatherAlpha method for tiled resources requires shader model 5 or higherTextureCube GatherCmpRed method for tiled resources requires shader model 5 or higherTextureCube GatherCmpGreen method for tiled resources requires shader model 5 or higherTextureCube GatherCmpBlue method for tiled resources requires shader model 5 or higherTextureCube GatherCmpAlpha method for tiled resources requires shader model 5 or higherTexture1DArray Load method for tiled resources requires shader model 5 or higherTexture1DArray Sample method for tiled resources requires shader model 5 or higherTexture1DArray SampleCmp method for tiled resources requires shader model 5 or higherTexture1DArray SampleCmpLevelZero method for tiled resources requires shader model 5 or higherTexture1DArray SampleLevel method for tiled resources requires shader model 5 or higherTexture1DArray SampleBias method for tiled resources requires shader model 5 or higherTexture2DArray Load method for tiled resources requires shader model 5 or higherTexture2DArray Sample method for tiled resources requires shader model 5 or higherTexture2DArray SampleCmp method for tiled resources requires shader model 5 or higherTexture2DArray SampleCmpLevelZero method for tiled resources requires shader model 5 or higherTexture2DArray SampleLevel method for tiled resources requires shader model 5 or higherTexture2DArray SampleBias method for tiled resources requires shader model 5 or higherTexture2DArray Gather method for tiled resources requires shader model 5 or higherTexture2DArray GatherGreen method for tiled resources requires shader model 5 or higherTexture2DArray GatherBlue method for tiled resources requires shader model 5 or higherTexture2DArray GatherAlpha method for tiled resources requires shader model 5 or higherTexture2DArray GatherCmpRed method for tiled resources requires shader model 5 or higherTexture2DArray GatherCmpGreen method for tiled resources requires shader model 5 or higherTexture2DArray GatherCmpBlue method for tiled resources requires shader model 5 or higherTexture2DArray GatherCmpAlpha method for tiled resources requires shader model 5 or higherTextureCubeArray Sample method for tiled resources requires shader model 5 or higherTextureCubeArray SampleCmp method for tiled resources requires shader model 5 or higherTextureCubeArray SampleCmpLevelZero method for tiled resources requires shader model 5 or higherTextureCubeArray SampleLevel method for tiled resources requires shader model 5 or higherTextureCubeArray SampleBias method for tiled resources requires shader model 5 or higherTextureCubeArray GatherRed method for tiled resources requires shader model 5 or higherTextureCubeArray GatherGreen method for tiled resources requires shader model 5 or higherTextureCubeArray GatherBlue method for tiled resources requires shader model 5 or higherTextureCubeArray GatherAlpha method for tiled resources requires shader model 5 or higherTextureCubeArray GatherCmpRed method for tiled resources requires shader model 5 or higherTextureCubeArray GatherCmpGreen method for tiled resources requires shader model 5 or higherTextureCubeArray GatherCmpBlue method for tiled resources requires shader model 5 or higherTextureCubeArray GatherCmpAlpha method for tiled resources requires shader model 5 or higherGatherGreen requires shader model 5 or higherGatherBlue requires shader model 5 or higherGatherAlpha requires shader model 5 or higherTessellation factor scale will be clamped to the range [0, 1]Tess factor processing functions only available on shader model 4+%s does not support msad4function '%s' missing implementationflow control depth too deep to emit function calllate-resolve interface calls nested too deeplyinterface references must resolve to non-varying objectsabstract interfaces not supported on %s, interface references must resolve to specific instancesinternal error: failed to devirtualize a contained interface callno classes implement '%s'D3D11 Assembler Error: Invalid Bytecode: %sD3D11 Internal Compiler Error: Invalid Bytecode: %sValidation Error: %sBytecode appears corrupt - integrity check failed.Failed to extract driver shader code.Failed to extract input signature.Failed to extract output signature.Input signature cannot be defined for a library function.Output signature cannot be defined for a library function.ShaderFeatureInfo blob must not specify 4x raw and structured buffers for Compute Shaders, or for any shader 5_0+.Failed to extract patch constant signature.Unrecognized shader type.Failed to parse shader using reference shader parser: 0x%xInvalid interface metadata: too many instances.Invalid interface metadata: too many types.Invalid interface metadata: too many interface slots.Invalid interface metadata: no types defined.Invalid interface metadata: instance buffer overrun.Invalid interface metadata: type buffer overrun.Invalid interface metadata: interface buffer overrun.Invalid interface metadata: interface %u unimplemented.Invalid interface metadata: duplicated type in interface %d's type list.Invalid interface metadata: interface count mismatch.Invalid interface metadata: type %d violates type stride limits.Invalid interface metadata: type name buffer overrun.Invalid interface metadata: unterminated type name.Invalid interface metadata: instance type buffer overrun.Invalid interface metadata: variable %d violates limits on member offsets.Invalid interface metadata: instance name buffer overrun.Invalid interface metadata: unterminated instance name.Can't continue validation - aborting.label (%d) already defined. Opcode #%d (count 1-based). function body (%d) defined without being declared. Opcode #%d (count 1-based). function body (%d) referenced without being defined. Opcode #%d (count 1-based). function body (%d) already declared. Opcode #%d (count 1-based). Declaration statements must appear before other instructions.%s instruction requires shader model 5 or higher.Incorrect number of operands for opcode #%d (count is 1-based).  Expecting %d, encountered %d.Saturate modifier not permitted for opcode #%d (counts are 1-based). Precise mask not permitted for opcode #%d (counts are 1-based). Resource dimension and return type extended opcodes not expected on opcode #%d (counts are 1-based). Invalid operand type for operand #%d of opcode #%d (counts are 1-based). Expected component count of 0 for operand #%d of opcode #%d (counts are 1-based). Expected component count of 1 (or 4 component with select-1 mode) for operand #%d of opcode #%d (counts are 1-based). Expected component count of 4 (or 1 component immediate32, or in certain cases NULL or scalar operand allowed) for operand #%d of opcode #%d (counts are 1-based). Expected nonzero component mask (or in certain cases also NULL or single component output operand allowed) for operand #%d of opcode #%d (counts are 1-based). Expected single component mask (or in certain cases also NULL or single component output operand allowed) for operand #%d of opcode #%d (counts are 1-based). Expected contiguous component mask starting at x (.x, .xy, .xyz, or .xyzw) for operand #%d of opcode #%d (counts are 1-based). Expected a component mask which picks any one or 2 components for operand #%d of opcode #%d (counts are 1-based). Expected double-compatible component mask (xy, zw, or xyzw) for operand #%d of opcode #%d (counts are 1-based). Expected double-compatible swizzle for operand #%d of opcode #%d (counts are 1-based). Negate modifier not allowed for operand #%d of opcode #%d (counts are 1-based). Abs modifier not allowed for operand #%d of opcode #%d (counts are 1-based). .rrrr swizzle expected for operand #%d of opcode #%d (counts are 1-based). Incompatible min precision type for operand #%d of opcode #%d (counts are 1-based). Expected float.Unrecognized min precision type for operand #%d of opcode #%d (counts are 1-based).Incompatible min precision type for operand #%d of opcode #%d (counts are 1-based). Expected int or uint.Min precision types not allowed for operand #%d of opcode #%d (counts are 1-based). Only immediate32 indexing permitted for operand #%d of opcode #%d (counts are 1-based). Aborting.Indexing of t# resources with current instruction requires opcode to specify resource dimension and return type. Operand #%d of opcode #%d (counts are 1-based). Aborting.4 component with no swizzle expected for operand #%d of opcode #%d (counts are 1-based). Constant buffer size (%d 16-byte entries) exceeds allowed limit of %d entries. Aborting.Unexpected indexing dimension for operand #%d of opcode #%d (counts are 1-based). Aborting.Invalid indexing mode for first dimension.  Opcode #%d, operand #%d (counts are 1-based). Invalid index dimension %d for relative address temp register within dimension 1 of operand.  Opcode #%d, operand #%d (counts are 1-based). Index Dimension %d's relative address temp is out of range (%d specified, max allowed is %d) for operand #%d of opcode #%d (counts are 1-based). Aborting.Invalid index dimension for relative address indexable temp register within dimension %d of operand.  Opcode #%d, operand #%d (counts are 1-based). Index Dimension %d's relative address indexable temp is out of range (%d specified, max allowed is %d) for operand #%d of opcode #%d (counts are 1-based). Aborting.Index Dimension %d's relative address indexable temp index1 is out of range (%d specified, max allowed is %d) for operand #%d of opcode #%d (counts are 1-based). Aborting.Invalid relative indexing register type for dimension %d.  Operand #%d of opcode #%d (counts are 1-based). Aborting.Index Dimension %d out of range (%d specified, max allowed is %d) for operand #%d of opcode #%d (counts are 1-based). Aborting.Invalid representation for index dimension %d.  Opcode #%d, operand #%d (counts are 1-based). function body (%d) was never referenced.function body (%d) was never defined.function table (%d) was declared, but never referenced.Interface metadata instance %d refers to undeclared constant buffer %d.Interface metadata instance %d refers to undeclared constant buffer offset [%d,%d].Interface metadata instance %d refers to undeclared texture %d.Interface metadata instance %d refers to undeclared sampler %d.Interface metadata expects interface %d to be declared, but it was not.Interface metadata expects interface %d to be of size %d, but it was declared as size %d.interface pointer (%d) was declared, but never referenced.GS input primitive not declared. GS has no input primitive, so no input regisers may be declared.  Input v[][%d] was declared.All GS input v[][] registers must have vertex count (first dimension) declared with size equal to the number of vertices in the declared input primitive (%d vertices in this case). Input %d has %d vertices declared. GS output topology not declared for stream m%d. Interpolation mode for PS input position must be linear_noperspective_centroid or linear_noperspective_sample when outputting oDepthGE or oDepthLE and not running at sample frequency (which is forced by inputting SV_SampleIndex or declaring an input linear_sample or linear_noperspective_sample). Compute Shader must declare a thread group size (X,Y,Z).Thread local temp register storage in Compute Shader (per thread) %d. The shader declares too much temp storage (%d registers). For Compute Shader versions < 5_0, the element count for all Structured Thread Group Shared Memory declarations 
must be equal to the number of threads in the group (%d in this case).  %d elements were specified for g%d. For Compute Shader versions < 5_0, with %d threads in a group, at most %d bytes per thread of Thread Group Shared Memory 
can be declared (the amount is a function of how many threads there are).  This shader exceeds the limit at %d bytes per thread. 
Domain Shader must declare an input control point count.Domain Shader must declare a tessellator domain.Domain Shader input vDomain must be declared with at most a .xyz mask when the domain is TRI.Domain Shader input vDomain must be declared with at most a .xy mask when the domain is QUAD.Domain Shader input vDomain must be declared with at most a .xy mask when the domain is ISOLINE.All DS input control point vcp[][] registers must have control point count (first dimension) declared with size equal to the number of input control points declared in the hs decls phase (%d control points in this case). Input %d has %d control points declared. Total number of scalars across all DS input control points must not exceed %d. Current input control point declaration specifies %d scalars of output per control point with %d output control points, resulting in %d total scalars of input control point data. Input index range defined from %d to %d does not include any declared input registers. []Registers in an input index range cannot have system names associated with them (TessFactors are an exception).  Input register %s[%d] has a name and is in an index range from %d to %d. Masks (and if pixel shader, also interpolation mode) on all input registers in an index range must be identical. Input register %s[%d] does not match with others in the index range from %d to %d. Named register components cannot appear to the left (xyzw order) of components that are not named in a given register. TessFactors are an exception. Affected register is input %d. Named register components cannot appear to the left (xyzw order) of components that are not named in a given register. TessFactors are an exception. Affected register is output %d in stream m%d. Named register components cannot appear to the left (xyzw order) of components that are not named in a given register. TessFactors are an exception. Affected register is output %d. Mismatch between shader declaration of double precision floats and accompanying Shader Feature Info blob (or lack thereof). Both the shader must declare double precision float use and a Shader Feature Info blob must specify the same thing as well, or neither should request it. Mismatch between shader declaration of raw and structured buffers for shader 4_x and accompanying Shader Feature Info blob (or lack thereof). Both the shader must declare raw and structured buffer use and a Shader Feature Info blob must specify the same thing as well, or neither should request it. Mismatch between shader declaration of minimum precision and accompanying Shader Feature Info blob (or lack thereof). Both the shader must declare minimum precision use and a Shader Feature Info blob must specify the same thing as well, or neither should request it. Minimum precision types used in a shader that does not have minimum precision support enabled. Mismatch between shader declaration of 11.1 double extensions and accompanying Shader Feature Info blob (or lack thereof). Both the shader must declare 11.1 double extensions use and a Shader Feature Info blob must specify the same thing as well, or neither should request it. Mismatch between shader declaration of 11.1 double extensions and shader declaration of double precision floats. If a shader declares 11.1 double extensions use it must also declare double precision float use. Mismatch between shader declaration of 11.1 shader extensions and accompanying Shader Feature Info blob (or lack thereof). Both the shader must declare 11.1 shader extensions use and a Shader Feature Info blob must specify the same thing as well, or neither should request it. Raw or Structured buffers can't be declared in shader model 4_* VS/GS/PS without enabling them via a global flags declaration.. CB[%d] already declared, repeated declaration on opcode #%d (count is 1-based). Immediate constant buffer already declared, repeated declaration on opcode #%d (count is 1-based). Immediate constant buffer size must be a multiple (not incl. 0) of 32bit*4-tuples in size, but no larger than %d 32bit*4-tuples (%d bytes declared).  Opcode #%d (count is 1-based). Temp decl already encountered.  Repeated declaration on opcode #%d (count is 1-based). Too many temp registers declared (%d).  Max allowed is %d.  Opcode #%d (count is 1-based). Sum of temp registers and indexable temp registers exceeds limit of %d..  Opcode #%d (count is 1-based). Indexable temp register index, [%d], too high.  Opcode #%d (count is 1-based). Aborting.Indexable temp x%d already declared.  Opcode #%d (count is 1-based). Sum of temp registers and indexable temp registers exceeds limit of %d..  Opcode #%d (count is 1-based). Aborting. Invalid component mask in indexable temp decl: 0x%x.  Opcode #%d (count is 1-based). Aborting. Resource t%d already declared.  Opcode #%d (count is 1-based). Expected sample count of 0 but encountered %d for resource t%d.  Opcode #%d (count is 1-based). Texture2DMS resources are only available for input to Pixel Shaders. Opcode #%d (count is 1-based). Expected sample count > 0 but encountered %d for resource t%d.  Opcode #%d (count is 1-based). Invalid resource dimension on resource t%d.  Opcode #%d (count is 1-based). Invalid resource return type on component %d of resource t%d.  Opcode #%d (count is 1-based). Sampler s%d already declared.  Opcode #%d (count is 1-based). Invalid sampler mode on sampler s%d.  Opcode #%d (count is 1-based). The first stream declaration cannot appear after any output or output topology declarations.  Opcode #%d (count is 1-based). Invalid stream index s%d.  Index must be between 0 and %d Opcode #%d (count is 1-based). Stream s%d already declared.  Opcode #%d (count is 1-based). Input index range declaration out of range.  Opcode #%d (count is 1-based). Overlapping input index range decl encountered.  Opcode #%d (count is 1-based). Output index range declaration out of range.  Opcode #%d (count is 1-based). Overlapping output index range decl encountered.  Opcode #%d (count is 1-based). GS output topology in stream m%d already declared.  Opcode #%d (count is 1-based). GS output topology already declared.  Opcode #%d (count is 1-based). GS output primitive topology unrecognized.  Opcode #%d (count is 1-based). GS output vertex count declaration can't be more than %d vertices (%d specified).  Opcode #%d (count is 1-based). GS instance count already declared.  Opcode #%d (count is 1-based). GS instance count declaration cannot be greater than %d (%d specified).  Opcode #%d (count is 1-based). GS instance count must be at least 1 (%d specified).  Opcode #%d (count is 1-based). GS input primitive already declared.  Opcode #%d (count is 1-based). GS input primitive can be a patch only if the GS version is gs_5_0 and greater.  Opcode #%d (count is 1-based). GS input primitive unrecognized.  Opcode #%d (count is 1-based). vCycleCounter is only supported on 5_0+ shaders.  Opcode #%d (count is 1-based). Cycle Counter already declared.  Opcode #%d (count is 1-based). Cycle Counter declaration must have mask of .x or .xy.  Opcode #%d (count is 1-based). Compute Shader input Thread ID already declared.  Opcode #%d (count is 1-based). Compute Shader input Thread ID declaration must have a non-empty mask and allows only components x, y, and z in mask.  Opcode #%d (count is 1-based). Compute Shader input Thread Group ID already declared.  Opcode #%d (count is 1-based). Compute Shader input Thread Group ID declaration must have a non-empty mask and allows only components x, y, and z in mask.  Opcode #%d (count is 1-based). Compute Shader input Thread ID In Group already declared.  Opcode #%d (count is 1-based). Compute Shader input Thread ID In Group declaration must have a non-empty mask and allows only components x, y, and z in mask.  Opcode #%d (count is 1-based). Compute Shader input Thread ID In Group Flattened already declared.  Opcode #%d (count is 1-based). Compute Shader input Thread ID In Group Flattened declaration must have an empty writemask.  Opcode #%d (count is 1-based). Input primitive ID already declared in this HS phase.  Opcode #%d (count is 1-based). Hull Shader output control point ID already declared.  Opcode #%d (count is 1-based). Hull Shader fork phase instance ID already declared.  Opcode #%d (count is 1-based). Hull Shader join phase instance ID already declared.  Opcode #%d (count is 1-based). When there is no Control Point phase in the HS, the control points are pass-through to the DS, but the Fork/Join phases in the HS cannot use 'output control points' (vocp[][] registers).  Instead just use vcp[][] input control points (which are the same anyway in the passthrough case). Opcode #%d (count is 1-based).Input primitive ID already declared.  Opcode #%d (count is 1-based). Input domain point already declared.  Opcode #%d (count is 1-based). Input domain point declaration can't have an empty mask.  Opcode #%d (count is 1-based). GS input primID already declared.  Opcode #%d (count is 1-based). GS instance ID already declared.  Opcode #%d (count is 1-based). PS input vCoverage already declared.  Opcode #%d (count is 1-based). PS input vInnerCoverage declared, cannot also declare vCoverage (features are mutually exclusive).  Opcode #%d (count is 1-based). PS input vInnerCoverage requires feature flag enableInnerCoverage.  Opcode #%d (count is 1-based). PS input vInnerCoverage already declared.  Opcode #%d (count is 1-based). PS input vCoverage declared, cannot also declare vInnerCoverage (features are mutually exclusive).  Opcode #%d (count is 1-based). Components of input declaration for register %d overlap with previous declaration for same register.  Opcode #%d (count is 1-based). Invalid name or shader for SGV dcl.  Opcode #%d (count is 1-based). SGV must have scalar mask in declaration.  Opcode #%d (count is 1-based). vertexID already declared for input.  Opcode #%d (count is 1-based). instanceID already declared for input.  Opcode #%d (count is 1-based). Invalid name or shader for SIV dcl.  Opcode #%d (count is 1-based). TessFactors must each be declared with a single component.  Opcode #%d (count is 1-based). finalQuad*TessFactor requires QUAD tessellator domain.  Opcode #%d (count is 1-based). finalTri*TessFactor requires TRI tessellator domain.  Opcode #%d (count is 1-based). finalLine*TessFactor requires ISOLINE tessellator domain.  Opcode #%d (count is 1-based). finalQuadUeq0EdgeTessFactor already declared for input.  Opcode #%d (count is 1-based). finalQuadVeq0EdgeTessFactor already declared for input.  Opcode #%d (count is 1-based). finalQuadUeq1EdgeTessFactor already declared for input.  Opcode #%d (count is 1-based). finalQuadVeq1EdgeTessFactor already declared for input.  Opcode #%d (count is 1-based). finalQuadUInsideTessFactor already declared for input.  Opcode #%d (count is 1-based). finalQuadVInsideTessFactor already declared for input.  Opcode #%d (count is 1-based). finalTriUeq0EdgeTessFactor already declared for input.  Opcode #%d (count is 1-based). finalTriVeq0EdgeTessFactor already declared for input.  Opcode #%d (count is 1-based). finalTriWeq0EdgeTessFactor already declared for input.  Opcode #%d (count is 1-based). finalTriInsideTessFactor already declared for input.  Opcode #%d (count is 1-based). finalLineDetailTessFactor already declared for input.  Opcode #%d (count is 1-based). finalLineDensityTessFactor already declared for input.  Opcode #%d (count is 1-based). position already declared for input.  Opcode #%d (count is 1-based). Too many unique registers contain clip/cull distance values.  At most %d unique registers can have clip/cull distance in components.  Opcode #%d (count is 1-based). Too many total clip/cull distance values.  At most %d allowed (clip+cull total).  Opcode #%d (count is 1-based). Components of input declaration for register v%d overlap with previous declaration for same register.  Opcode #%d (count is 1-based). Invalid interpolation mode for register v%d.  Opcode #%d (count is 1-based). Interpolation mode cannot vary for different components of a single input register (v%d).  Opcode #%d (count is 1-based). primitiveID already declared for input.  Opcode #%d (count is 1-based). isFrontFace already declared for input.  Opcode #%d (count is 1-based). sampleIndex already declared for input.  Opcode #%d (count is 1-based). Interpolation mode for PS SGV must be constant (register v%d).  Opcode #%d (count is 1-based). Interpolation mode for PS input position must be linear_noperspective or linear_noperspective_centroid (shader model 4.1+ allows linear_noperspective_sample as well). Interpolation mode for PS clip or cull distance must be linear or linear centroid, or in 4.1, linear_sample  (register v%d).  Opcode #%d (count is 1-based). renderTargetArrayIndex or viewportArrayIndex must have scalar mask in declaration.  Opcode #%d (count is 1-based). renderTargetArrayIndex already declared for input.  Opcode #%d (count is 1-based). viewportArrayIndex already declared for input.  Opcode #%d (count is 1-based). Interpolation mode for PS renderTargetArrayIndex or viewportArrayIndex must be constant (register v%d).  Opcode #%d (count is 1-based). PS output depth already declared.  Opcode #%d (count is 1-based). PS output depth already declared.  The previous declaration was of a different type.  Opcode #%d (count is 1-based). PS output coverage mask already declared.  Opcode #%d (count is 1-based). PS output stencil ref requires feature flag enableStencilRef.  Opcode #%d (count is 1-based). PS output stencil ref already declared.  Opcode #%d (count is 1-based). PS ouputs must be declared in slots less than UAVs.  Output declared in slot %d while UAV declared in slot %d.  Opcode #%d (count is 1-based). Components of output declaration for register o%d overlap with previous declaration for same register.  Opcode #%d (count is 1-based). Components of output declaration for register %d overlap with previous declaration for same register.  Opcode #%d (count is 1-based). primitiveID already declared for output.  Opcode #%d (count is 1-based). isFrontFace already declared for output.  Opcode #%d (count is 1-based). finalQuadUeq0EdgeTessFactor already declared for output.  Opcode #%d (count is 1-based). finalQuadVeq0EdgeTessFactor already declared for output.  Opcode #%d (count is 1-based). finalQuadUeq1EdgeTessFactor already declared for output.  Opcode #%d (count is 1-based). finalQuadVeq1EdgeTessFactor already declared for output.  Opcode #%d (count is 1-based). finalQuadUInsideTessFactor already declared for output.  Opcode #%d (count is 1-based). finalQuadVInsideTessFactor already declared for output.  Opcode #%d (count is 1-based). finalTriUeq0EdgeTessFactor already declared for output.  Opcode #%d (count is 1-based). finalTriVeq0EdgeTessFactor already declared for output.  Opcode #%d (count is 1-based). finalTriWeq0EdgeTessFactor already declared for output.  Opcode #%d (count is 1-based). finalTriInsideTessFactor already declared for output.  Opcode #%d (count is 1-based). finalLineDetailTessFactor already declared for output.  Opcode #%d (count is 1-based). finalLineDensityTessFactor already declared for output.  Opcode #%d (count is 1-based). position declaration must have xyzw mask.  Opcode #%d (count is 1-based). position already declared for output.  Opcode #%d (count is 1-based). renderTargetArrayIndex already declared for output.  Opcode #%d (count is 1-based). viewportArrayIndex already declared for output.  Opcode #%d (count is 1-based). Global flags already declared once.  Opcode #%d (count is 1-based). Unrecognized global flags.  Opcode #%d (count is 1-based). enableRawAndStructuredBuffers global flag can't be used (not needed) with Compute Shaders.  Opcode #%d (count is 1-based). When streams are declared, you must use emit_stream, cut_stream, and emitthencut_stream instead of emit, cut, and emitthencut.  Opcode #%d (count is 1-based). Input control point count must be [%d..%d].  %d specified.  Opcode #%d (count is 1-based). Hull Shader input control point count already declared. Aborting.  Opcode #%d (count is 1-based). Input control point count must be [0..%d].  %d specified.  Opcode #%d (count is 1-based). Domain Shader input control point count already declared. Aborting.  Opcode #%d (count is 1-based). Hull Shader output control point count already declared. Aborting.  Opcode #%d (count is 1-based). Output control point count must be [0..%d].  %d specified.  Opcode #%d (count is 1-based). Invalid Tessellator Domain specified. Must be isoline, tri or quad. Aborting. Opcode #%d (count is 1-based). Tessellator domain already declared. Aborting. Opcode #%d (count is 1-based). Invalid Tessellator Partitioning specified. Must be integer, pow2, fractional_odd or fractional_even. Aborting. Opcode #%d (count is 1-based). Tessellator Partitioning already declared. Aborting. Opcode #%d (count is 1-based). Invalid Tessellator Output Primitive specified. Must be point, line, triangleCW or triangleCCW. Aborting. Opcode #%d (count is 1-based). Tessellator Output Primitive already declared. Aborting. Opcode #%d (count is 1-based). Hull Shader output max tessfactor already declared. Aborting.  Opcode #%d (count is 1-based). Hull Shader MaxTessFactor must be [%f..%f].  %f specified.  Opcode #%d (count is 1-based). Hull Shader Fork Phase Instance Count already declared in this phase. Aborting.  Opcode #%d (count is 1-based). Hull Shader Fork Phase Instance Count must be [%d..%d].  %d specified.  Opcode #%d (count is 1-based). Hull Shader Join Phase Instance Count already declared in this phase. Aborting.  Opcode #%d (count is 1-based). Hull Shader Join Phase Instance Count must be [%d..%d].  %d specified.  Opcode #%d (count is 1-based). Declared Thread Group X size %d outside valid range [%d..%d].  Opcode #%d (count is 1-based). Declared Thread Group Y size %d outside valid range [%d..%d].  Opcode #%d (count is 1-based). Declared Thread Group Z size %d outside valid range [%d..%d].  Opcode #%d (count is 1-based). Declared Thread Group Count %d (X*Y*Z) is beyond the valid maximum of %d.  Opcode #%d (count is 1-based). Declared Thread Group X size %d outside valid range [%d..%d] for Compute Shader version < 5_0.  Opcode #%d (count is 1-based). Declared Thread Group Y size %d outside valid range [%d..%d] for Compute Shader version < 5_0.  Opcode #%d (count is 1-based). Declared Thread Group Count %d (X*Y*Z) is beyond the valid maximum of %d for Compute Shader version < 5_0.  Opcode #%d (count is 1-based). SRV reference t%d must have a structure byte stride that is a multiple of 4 that is greater than 0 but no greater than %d when declared as structured (%d specified).  Opcode #%d (count is 1-based). Texture2DMS[Array] or TextureCube[Array] resources are not supported with UAVs (Unordered Access Views). Opcode #%d (count is 1-based). Invalid resource dimension on resource u%d.  Opcode #%d (count is 1-based). UAV u%d already declared.  Opcode #%d (count is 1-based). UAVs must be declared in slots greater than PS outputs.  UAV declared in slot %d while output declared in slot %d.  Opcode #%d (count is 1-based). Invalid resource return type on component %d of resource u%d.  Opcode #%d (count is 1-based). UAV reference u%d specified with invalid flag.  Opcode #%d (count is 1-based). UAV reference u%d: order preserving counter flag valid only on structured buffers.  Opcode #%d (count is 1-based). UAV reference u%d: ROV requires Rasterizer Ordered feature flag.  Opcode #%d (count is 1-based). UAV reference u%d must have a structure byte stride that is a multiple of 4 that is greater than 0 but no greater than %d when declared as structured (%d specified).  Opcode #%d (count is 1-based). UAV reference u%d has invalid flag.  Opcode #%d (count is 1-based). Thread Group Shared Memory reference g%d already declared.  Opcode #%d (count is 1-based). Thread Group Shared Memory reference g%d byteCount (%d specified) must be a nonzero multiple of 4.  Opcode #%d (count is 1-based). Total Thread Group Shared Memory storage exceeded by g# declarations so far up to g%d.  Opcode #%d (count is 1-based). Thread Group Shared Memory reference g%d must have a structure byte stride that is a nonzero multiple of 4 when declared as structured (%d specified).  Opcode #%d (count is 1-based). Output index range defined from %d to %d includes output register %d that was not declared. Registers in an output index range cannot have system names associated with them (TessFactors are an exception).  Output register o%d has a name and is in an index range from o%d to o%d. The intersection of all masks on output registers in an index range cannot be empty. Index range from o%d to o%d has empty mask intersecion. Reference of undeclared temp r%d.  Opcode #%d, operand #%d (counts are 1-based). Reference out of range on vertex axis for input v[%d][].  Input primitive type has %d vertices.  Opcode #%d, operand #%d (counts are 1-based). Reference out of range on vertex axis for input v[%d][].  Input control point has %d vertices.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared input or undeclared components of input v%s[%d].  Opcode #%d, operand #%d (counts are 1-based). Relative indexing input register from base %s[0] not allowed when register 0 has not been declared in an index range.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared input or undeclared components of index range input starting at base v%s[%d].  Opcode #%d, operand #%d (counts are 1-based). Relative indexing input register from base %s[%d] not allowed when register %d has not been declared in an index range.  Opcode #%d, operand #%d (counts are 1-based). Reference out of range on vertex axis for input vcp[%d][].  Input control point has %d vertices.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared input or undeclared components of input vcp[][%d].  Opcode #%d, operand #%d (counts are 1-based). Relative indexing input register from base vcp[0] not allowed when register 0 has not been declared in an index range.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared input or undeclared components of index range input starting at base vcp[][%d].  Opcode #%d, operand #%d (counts are 1-based). Relative indexing input register from base vcp[][%d] not allowed when register %d has not been declared in an index range.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared input or undeclared components of input vpc[%d].  Opcode #%d, operand #%d (counts are 1-based). Relative indexing input register from base vpc[0] not allowed when register 0 has not been declared in an index range.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared input or undeclared components of index range input starting at base vpc[%d].  Opcode #%d, operand #%d (counts are 1-based). Relative indexing input register from base vpc[%d] not allowed when register %d has not been declared in an index range.  Opcode #%d, operand #%d (counts are 1-based). Reference out of range on vertex axis for input vocp[%d][].  Output control points has %d vertices.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared input or undeclared components of input vocp[][%d].  Opcode #%d, operand #%d (counts are 1-based). Relative indexing input register from base vocp[][0] not allowed when register 0 has not been declared in an index range.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared input or undeclared components of index range input starting at base vocp[][%d].  Opcode #%d, operand #%d (counts are 1-based). Relative indexing input register from base vocp[][%d] not allowed when register %d has not been declared in an index range.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared output or undeclared components of output o%d.  Opcode #%d, operand #%d (counts are 1-based). Relative indexing output register from base o[0] not allowed when register 0 has not been declared in an index range.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared output or undeclared components of index range output starting at base o[%d].  Opcode #%d, operand #%d (counts are 1-based). Relative indexing output register from base o[%d] not allowed when register %d has not been declared in an index range.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared indexable temp x%d[].  Opcode #%d, operand #%d (counts are 1-based). Reference out of bounds, [%d], on x%d[size==%d].  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared components of indexable temp x%d[].  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared sampler s%d.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared stream m%d.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared resource t%d.  Opcode #%d, operand #%d (counts are 1-based). Reference out of bounds, cb%d.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared constant buffer cb%d[].  Opcode #%d, operand #%d (counts are 1-based). Reference out of bounds, [%d], on cb%d[size==%d] (if size is listed as 0, it means default size is used, which is %d.  Opcode #%d, operand #%d (counts are 1-based). Relative indexing not allowed for cb%d since it was not declared for dynamic indexing..  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared immediate constant buffer.  Opcode #%d, operand #%d (counts are 1-based). Reference out of bounds, [%d], on immediate constant buffer [size==%d].  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register vPrimitiveID.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register vGSInstanceID.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register oDepth.  Opcode #%d, operand #%d (counts are 1-based). Reference of register oDepth does mot match declaration (dcl_oDepthGE or dcl_oDepthLE).  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register oDepthGE.  Opcode #%d, operand #%d (counts are 1-based). Reference of register oDepthGE does mot match declaration (dcl_oDepth or dcl_oDepthLE).  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register oDepthLE.  Opcode #%d, operand #%d (counts are 1-based). Reference of register oDepthLE does mot match declaration (dcl_oDepth or dcl_oDepthGE).  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register vCoverage.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register vInnerCoverage.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register oMask.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register oStencilRef.  Opcode #%d, operand #%d (counts are 1-based). Invalid component selection mode for vCycleCounter.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared components of input vCycleCounter.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register vOutputControlPointID.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register vForkPhaseInstanceID.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared register vJoinPhaseInstanceID.  Opcode #%d, operand #%d (counts are 1-based). Invalid component selection mode for vInputThreadID.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared components of input vInputThreadID.  Opcode #%d, operand #%d (counts are 1-based). Invalid component selection mode for vInputThreadGroupID.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared components of input vInputThreadGroupID.  Opcode #%d, operand #%d (counts are 1-based). Invalid component selection mode for vInputThreadIDInGroup.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared components of input vInputThreadIDInGroup.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared input vInputThreadIDInGroupFlattened.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared UAV u%d.  Opcode #%d, operand #%d (counts are 1-based). Reference of undeclared thread group shared memory g%d[].  Opcode #%d, operand #%d (counts are 1-based). Reference out of bounds, [%d], on g%d[size==%d].  Opcode #%d, operand #%d (counts are 1-based). Index Dimension %d's relative address temp is out of range (%d specified, max allowed based on temp declaration is %d) for operand #%d of opcode #%d (counts are 1-based). Aborting.Reference of undeclared components of indexable temp x%d[] within relative index of an operand.  Opcode #%d, operand #%d (counts are 1-based). Reference out of range of indexable temp x%d[] within relative index of an operand.  Index [%d] specified, but based on the indexable temp declaration, the max index allowed is [%d].  Operand #%d of opcode #%d (counts are 1-based). Aborting.function table (%d) already declared. Opcode #%d (count 1-based). interface decl references undefined function table (%d).  Opcode #%d (count 1-based).interface decl expects a table of size %d, but table %d has %d elements.  Opcode #%d (count 1-based).interface decl for interface index %d has different function table data than the interface metadata.  Opcode #%d (count 1-based).interface decl declares an interface index %d that is not a base register in the interface metadata.  Opcode #%d (count 1-based).interface decl declares an interface index %d that is not the interface metadata.  Opcode #%d (count 1-based).interface decl declares an invalid interface index %d.  Opcode #%d (count 1-based).interface decl declares an interface index (%d) that has already been declared.  Opcode #%d (count 1-based).bufinfo requires resource declared as Buffer, Raw Buffer or Structured Buffer.  Opcode #%d, operand #%d (counts are 1-based). ld does not support raw or structured buffers.  Opcode #%d, operand #%d (counts are 1-based). ld requires resource declared as texture1D/2D/3D/1DArray/2DArray.  Opcode #%d, operand #%d (counts are 1-based). ld2dms requires resource declared as texture2DMS/texture2DMSArray.  Opcode #%d, operand #%d (counts are 1-based). lod instruction requires sampler declared in default mode.  Opcode #%d, operand #%d (counts are 1-based). lod requires resource declared as texture1D/2D/3D/Cube/CubeArray/1DArray/2DArray.  Opcode #%d, operand #%d (counts are 1-based). comparison%s instruction requires sampler declared in %s mode.  Opcode #%d, operand #%d (counts are 1-based). /Cube/CubeArray%s requires resource declared as texture2D/2DArray%s.  Opcode #%d, operand #%d (counts are 1-based). resinfo requires resource declared as texture1D/2D/3D/Cube/1DArray/2DArray/2DMS/2DMSArray.  Opcode #%d, operand #%d (counts are 1-based). sample/_l/_d/_cl_s instructions require sampler declared in default mode.  Opcode #%d, operand #%d (counts are 1-based). sample/_l/_d requires resource declared as texture1D/2D/3D/Cube/1DArray/2DArray.  Opcode #%d, operand #%d (counts are 1-based). sample_c_* instructions require sampler declared in comparison mode.  Opcode #%d, operand #%d (counts are 1-based). sample_c_* instructions require resource declared as texture1D/2D/Cube/1DArray/2DArray/CubeArray.  Opcode #%d, operand #%d (counts are 1-based). sample_c_* instructions require resource declared as texture1D/2D/Cube, but arrays not allowed.  Opcode #%d, operand #%d (counts are 1-based). sample_b requires sampler declared in default mode.  Opcode #%d, operand #%d (counts are 1-based). bias amount for sample_b must be in the range [%f,%f], but %f was specified as an immediate. Opcode #%d, operand #%d (counts are 1-based). sample_b requires resource declared as texture1D/2D/3D/Cube/1DArray/2DArray.  Opcode #%d, operand #%d (counts are 1-based). swapc requires destination registers to be different.  Opcode #%d, operand #1 and operand #2 (counts are 1-based).sync in a non-Compute Shader must only sync UAV (sync_uglobal).Opcode #%d (counts are 1-based).sync must include some form of memory barrier - _u (UAV) and/or _g (Thread Group Shared Memory).  Only _t (thread group sync) is optional. Opcode #%d (counts are 1-based).sync can't specify both _ugroup and _uglobal. If both are needed, just specify _uglobal. Opcode #%d (counts are 1-based).ld_uav_typed cannot be used on a UAV that is not declared as typed (u%d). Opcode #%d (counts are 1-based).store_uav_typed cannot be used on a UAV that is not declared as typed (u%d). Opcode #%d (counts are 1-based).store_uav_typed must write to all four components of the UAV. Opcode #%d (counts are 1-based).ld_raw requires resource declared as Raw Buffer.  Opcode #%d, operand #%d (counts are 1-based). ld_raw cannot be used on a resource that is not declared as raw (resource index [%d]). Opcode #%d (counts are 1-based).store_raw cannot be used on a resource that is not declared as raw (resource index [%d]). Opcode #%d (counts are 1-based).ld_structured requires resource declared as Structured Buffer.  Opcode #%d, operand #%d (counts are 1-based). ld_structured cannot be used on a resource that is not declared as structured (resource index [%d]). Opcode #%d (counts are 1-based).store_structured cannot be used on a resource that is not declared as structured (resource index [%d]). Opcode #%d (counts are 1-based).store_structured writing to Thread Group Shared Memory for shader models less than 5_0 must use 
vThreadIDInGroupFlattened as the structure index (second) parameter. Opcode #%d (counts are 1-based).imm_atomic_alloc and imm_atomic_consume require as Structured Buffer UAV (slot %d). Opcode #%d (counts are 1-based).imm_atomic_alloc and imm_atomic_consume on a given UAV (%d) cannot both be in the same shader. Opcode #%d (counts are 1-based).imm_atomic_alloc and imm_atomic_consume can't be combined with other atomic operations on an Append UAV (%d). Opcode #%d (counts are 1-based).sample_* instructions require resource to be declared to return UNORM, SNORM or FLOAT.  Opcode #%d, operand #%d (counts are 1-based). vCycleCounter can only be used with the mov instruction.  Opcode #%d, operand #%d (counts are 1-based). else statement doesn't match to an if statement. Opcode #%d (count 1-based). Aborting validation.else statement seen already.  Opcode #%d (count 1-based). Aborting validation.endif statement doesn't match to an if statement. Opcode #%d (count 1-based). Aborting validation.endloop statement doesn't match to a loop statement. Opcode #%d (count 1-based). Aborting validation.endswitch statement doesn't match to a switch statement. Opcode #%d (count 1-based). Aborting validation.case statement doesn't match to the scope of a switch statement. Opcode #%d (count 1-based). Aborting validation.case %d (or if bits to be interpreted as float: %f) already seen. Opcode #%d (count 1-based).default statement doesn't match to the scope of a switch statement. Opcode #%d (count 1-based). Aborting validation.default statement seen already.  Opcode #%d (count 1-based).continue/continuec statement not inside loop.  Opcode #%d (count 1-based).break/breakc statement not inside loop or switch.  Opcode #%d (count 1-based).call/callc statement not referencing a label.  Opcode #%d (count 1-based).Shader Model 5+ requires that subroutine definitions appear after any call(s) to the subroutine. This also implies recursion is not allowed, although that may or may not be the case here.  Aborting. Opcode #%d (count 1-based).Multiple Hull Shader phases cannot call the same subroutine. If this is an important feature, support could be considered in the future. Opcode #%d (count is 1-based)fcall statement not referencing an interface.  Opcode #%d (count 1-based).fcall statement referencing an undeclared interface (%d).  Opcode #%d (count 1-based).fcall statement referencing an out of bounds function index (%d).  Opcode #%d (count 1-based).shader exceeds maximum supported number of interface call sites (%d).  Opcode #%d (count 1-based).Multiple Hull Shader phases cannot call the same interface body. If this is an important feature, support could be considered in the future. Opcode #%d (count is 1-based)label (%d) being defined without any callers. Shader Model 5+ requires all callers to a subroutine to appear before the subroutine definition. Aborting.Opcode #%d (count 1-based). label (%d) was never used in the shaderlabel (%d) must be preceded by a ret. Opcode #%d (count 1-based). Aborting validation.label (%d) must not be nested inside flow control. Opcode #%d (count 1-based). Aborting validation.Interpolation mode on input v# register used with eval_* instruction must be linear, linear_centroid, linear_noperspective, linear_noperspective_centroid, linear_sample or linear_noperspective_sample. Opcode #%d (count is 1-based). It is invalid to use eval_* on position input due to hardware limitation.  Opcode #%d (count is 1-based). Can't fall through case/default unless case/default has no code. Opcode #%d (count 1-based). Aborting validation.switch must be followed by case or default. Opcode #%d (count 1-based). Aborting validation.ret can only be followed by case/default/endswitch/endloop/else/endif/label. Opcode #%d (count 1-based). Aborting validation.break/continue can only be followed by case/default/endswitch/endloop/else/endif. Opcode #%d (count 1-based). Aborting validation.label (%d) called but not defined.label (%d) defined but never called.End of program reached with incomplete flow control structure.When code ends in subroutine definition, it must end with ret.%s signature parameter %s (1-based Entry %d) specifies invalid interpolation mode for integer component type. %s signature parameter %s (1-based Entry %d) specifies unrecognized or invalid component type. %s array signature parameter %s cannot be indexed dynamically.Non system-generated input signature parameter (%s) cannot appear after a system generated value.%s signature parameter %s (1-based Entry %d) type must be float32. %s signature parameter %s (1-based Entry %d) type must be uint32. %s signature parameter %s (1-based Entry %d) type must be float32 and mask must be xyzw. Too many %s signature parameters of type SV_ClipDistance or SV_CullDistance.  Maximum number of registers usable is %i.%s signature parameter %s (1-based Entry %d) type must be a scalar uint. %s signature parameter %s (1-based Entry %d) type must be a scalar float. %s signature parameter %s (1-based Entry %d) has an unrecognized system name. Stream index (%u) must between 0 and %u.Patch constant signature parameter #%d (1-based) specifies out of range register %d. Patch constant signature parameter #%d (1-based) specifies register %d (or components in the register) that have already been defined. Patch constant signature name mismatch with declaration in shader code for component %d in register %d. Patch constant signature signature does not specify component %d of register %d which is declared in the shader code. Input signature parameter #%d (1-based) specifies out of range register %d. Input signature parameter #%d (1-based) specifies register %d (or components in the register) that have already been defined. Input signature name mismatch with declaration in shader code for component %d in register %d. Input signature does not specify component %d of register %d which is declared in the shader code. Output signature parameter #%d (1-based) specifies out of range register %d. Output signature parameter #%d (1-based) specifies register %d (or components in the register) that have already been defined. Output signature name mismatch with declaration in shader code for component %d in register %d. Output signature does not specify component %d of register %d which is declared in the shader code. Pixel Shader allows output semantics to be SV_Target, SV_Depth, SV_DepthGreaterEqual, SV_DepthLessEqual, SV_Coverage only, or SV_StencilRef.  Output signature parameter #%d (1-based) specifies semantic %s. Double operations not supported unless globalFlags includes enableDoublePrecisionFloatOps.Extended 11.1 double operations not supported unless globalFlags includes enable11_1DoubleExtensions.Extended 11.1 shader operations not supported unless globalFlags includes enable11_1ShaderExtensions.Unrecognized instruction or instruction not valid in vertex shader.Hull Shader declsphase must declare an input control point count.Hull Shader declsphase must declare an output control point count.Hull Shader declsphase must declare a tessellator domain.Hull Shader declsphase must declare a tessellator partitioning.Hull Shader declsphase must declare a tessellator output primitive.Hull Shader declared with IsoLine Domain must specify output primitive point or line. triangle_cw or triangle_ccw output are not compatible with the IsoLine Domain.Hull Shader declared with Tri Domain must specify output primitive point, triangle_cw or triangle_ccw. line output is not compatible with the Tri domain.Hull Shader declared with Quad Domain must specify output primitive point, triangle_cw or triangle_ccw. line output is not compatible with the Quad domain.All HS control point phase input v[][] registers must have control point count (first dimension) declared with size less than or equal to the number of input control points declared in the hs decls phase (%d control points in this case). Input %d has %d control points declared. Total number of scalars across all HS output control points must not exceed %d. Current output control point declaration specifies %d scalars of output per control point with %d output control points, resulting in %d total scalars of output control point data. All HS fork phase input vcp[][] registers must have control point count (first dimension) declared with size less than or equal to the number of input control points declared in the hs decls phase (%d control points in this case). Input %d has %d control points declared. All HS fork phase input vocp[][] registers must have control point count (first dimension) declared with size less than or equal to the number of output control points declared in the hs decls phase (%d control points in this case). Input %d has %d control points declared. Hull Shader Fork Phase reads component(s) of output control point [%d] which were not output by the Control Point Phase.Multiple fork phase programs declared the same component(s) of output patch constant register o[#d].Multiple fork phase programs cannot declare partially overlapping index ranges for output Patch Constant Data. One index range is from register [%d] to [%d], while the another is from [%d] to [%d].All HS join phase input vcp[][] registers must have control point count (first dimension) declared with size equal to the number of input control points declared in the hs decls phase (%d control points in this case). Input %d has %d control points declared. All HS join phase input vocp[][] registers must have control point count (first dimension) declared with size equal to the number of output control points declared in the hs decls phase (%d control points in this case). Input %d has %d control points declared. Hull Shader Join Phase reads component(s) of output control point [%d] which were not output by the Control Point Phase.Join phase declaring component(s) of input patch constant register vpc[%d] which have not been output by previous fork phase(s) or other join phase(s).Join phase declared the same component(s) of output patch constant register o[#d] as already declared for output by a previous fork phase or other joint phase.Multiple fork/join phase programs cannot declare partially overlapping index ranges for output Patch Constant Data. One index range is from register [%d] to [%d], while the another is from [%d] to [%d].When the Hull Shader doesn't have a Control Point Phase, the declared Input Control Point Count (%d) must match the declared Output Control Point Count (%d), indicating the control points will pass through, or the Output Control Point Count can be set 0. finalTriUEdgeTessFactorfinalTriVEdgeTessFactorfinalTriWEdgeTessFactorRelated TessFactor names (such as edges) must be declared in the same component of consecutive Patch Constant registers, in the correct order. %s is in %s[%d].%s, which would put %s past the end of the available registers, since it is %d name after %s in the order.Related TessFactor names (such as edges) must be declared in the same component of consecutive Patch Constant registers, in the correct order. %s expected in %s[%d].%s since %s is in %s[%d].%s.TRIQUADISOLINERequired TessFactor name %s for %s domain not found declared anywhere in Patch Constant data. Index ranges declared on Patch Constant Data cannot cross over related blocks of hardware TessFactors. An index range is declared from register [%d] to [%d], which crosses over a block of TessFactors that starts with %s in register [%d] and ends in %s in register [%d].Unrecognized instruction or instruction not valid in Hull Shader.Hull Shader must start with HSDecls phase.Invalid instruction for Hull Shader Decls phase.Declaration statements in HS Control Point phase must appear before other instructions.Invalid instruction for Hull Shader Control Point phase.Declaration statements in HS Fork phase must appear before other instructions.Invalid instruction for Hull Shader Fork phase.Declaration statements in HS Join phase must appear before other instructions.Invalid instruction for Hull Shader Join phase.Invalid instruction for Hull Shader postamble section (subroutines and function bodies).Unrecognized instruction or instruction not valid in Domain Shader.Unrecognized instruction or instruction not valid in geometry shader.Declared output vertex count (%d) multiplied by the total number of declared scalar components of output data (%d) equals %d.  This value cannot be greater than %d.Unrecognized instruction or instruction not valid in pixel shader.Dest register relative index temp register component %d in r%d uninitialized. Opcode #%d (count is 1-based)Dest register relative index indexable-temp register component %d in x[%d][%d] uninitialized. Opcode #%d (count is 1-based)source register relative index temp register component %d in r%d uninitialized. Opcode #%d (count is 1-based)source register relative index indexable-temp register component %d in x[%d][%d] uninitialized. Opcode #%d (count is 1-based)source component %d in temp r%d not initialized. Opcode #%d (count is 1-based)source indexable temp register component %d in x%d[*] never initialized anywhere.Opcode #%d (count is 1-based)Unrecognized instruction or instruction not valid in Compute Shader.Unrecognized instruction or instruction not valid in a library function.


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&')	#*(%(	%(	(	((		((		((	(	(	(%cs_%d_%dlib_4_0_level_9_1_vslib_4_0_level_9_3_vslib_4_0_level_9_1_ps%s(%d) : (Statement %d) Out of memory.r/g/b/a/x/y/z/w/0 1 2 3IDirect3DShaderValidator9::Begin called out of order. ::End must be called first.IDirect3DShaderValidator9::Instruction called out of order. ::Begin must be called first.IDirect3DShaderValidator9::Instruction called out of order. After end token there should be no more instructions.  Call ::End next.IDirect3DShaderValidator9::Instruction called with NULL == pdwInst or 0 == cdw.Bad version token.  DWORD count > 1 given. Expected DWORD count to be 1 for version token.Bad version token.  It indicates neither a pixel shader nor a vertex shader.Bad end token.  DWORD count > 1 given. Expected DWORD count to be 1 for end token.IDirect3DShaderValidator9::End called out of order. Call to ::Begin, followed by calls to ::Instruction must occur first.Shader missing end token.Version token 0x%x does not represent a pixel library function.Out of memoryVersion token 0x%x does not represent a vertex shader.Version token 0x%x does not represent a vertex library function.ZMhZGDirect3D9: Shader Validator: Version Token: 0x%x indicates a vertex shader.  Pixel shader version token must be of the form 0xffff****.Version Token: 0x%x is invalid. Pixel shader version token must be of the form 0xffff****. Aborting pixel shader validation.Version Token: Shader version %s is not supported by hardware. ps_1_0 is no longer supported.  It turned out that pixel shader capable hardware will always support at least ps_1_1 (which is not as limited a model as ps_1_0 was). To convert a ps_1_0 shader up to ps_1_1, the only change needed is to make the version number 1_1. Version Token: Shader version %s is not supported. Aborting pixel shader validation.Instruction not supported by %s shader.Invalid parameter count.firstsecondthird(%s source param) Modifiers are not allowed on constants for ps_1_x.Second source parameter for texm3x3spec must be c#.Src reg for tex* instruction must be t# register (%s source param).Invalid reg type (%s source param).Invalid reg num %d (%s source param).  Max allowed for this type is %d._bx2 is a valid src mod for texM* instructions only (%s source param)._bx2 cannot be used on src register for texreg2ar or texreg2gb instructions._bx2 cannot be used on src register for texbem or texbeml instructions.Invalid src mod for tex* instruction (%s source param).Source swizzle not allowed for tex* instruction (%s source param).Invalid reg type for %s source param.Invalid reg num: %d for %s source param. Max allowed for this type is %d.For ps_1_2 or ps_1_3, the cmp or dp4 instructions cannot have a source register the same as the destination register.Invalid src mod for %s source param.Src selector .b (%s source param) is only valid for instructions that occur in the alpha pipe.Invalid src swizzle for %s source param.Cannot apply a negation source modifier on data that was last written with the saturate destination modifier. Affected components(*) of %s source param: %sWhen using the bias source modifier on a register, the previous writer should apply the saturate modifier. This would ensure consistent behaviour across different hardware. Affected components(*) of %s source param: %sWhen using the complement source modifier on a register, the previous writer should apply the saturate destination modifier. This would ensure consistent behaviour across different hardware. Affected components(*) of %s source param: %s, texm3x2depthTexture register result of texkill%s or texm*pad instructions must not be read. Affected components(*) of %s source param: %sTexture register result of texbem or texbeml instruction must not be read by tex* instruction. Affected components(*) of %s source param: %sRegister data that has been read by a texbem or texbeml instruction cannot be read later, except by another texbem/l.Multiple dependent texture reads are disallowed (%s source param).  Texture read results can be used as an address for subsequent read, but the results from that read cannot be used as an address in yet another subsequent read.Read of uninitialized component%s(*) in %s%d: %sInvalid reg type for dest param.Invalid dest reg num: %d. Max allowed for this reg type is %d.Destination of texm3x2depth instruction (t%d) is not available elsewhere in shader.Must use texture register a dest param for tex* instructions.tex* instructions must write all components.Instruction modifiers are not allowed for tex* instructions.Dest shift not allowed for tex* instructions.Invalid dst modifier.Invalid dst shift.Dest write mask must be .rgb, .a, or .rgba (all).%d different temp registers (r#) read by instruction.  Max. different temp registers readable per instruction is %d.%d different input registers (v#) read by instruction.  Max. different input registers readable per instruction is %d.%d different constant registers (c#) read by instruction.  Max. different constant registers readable per instruction is %d.%d different texture registers (t#) read by instruction.  Max. different texture registers readable per instruction is %d.%d different temp registers (r#) read over 2 co-issued instructions. Max. different register numbers from any one register type readable across co-issued instructions is %d.%d different input registers (v#) read over 2 co-issued instructions. Max. different register numbers from any one register type readable across co-issued instructions is %d.%d different constant registers (c#) read over 2 co-issued instructions. Max. different register numbers from any one register type readable across co-issued instructions is %d.%d different texture registers (t#) read over 2 co-issued instructions. Max. different register numbers from any one register type readable across co-issued instructions is %d.Tex register t%d already declared.t# registers must appear in sequence (i.e. t0 before t2 OK, but t1 before t0 not valid).Cannot use tex* instruction after non-tex* instruction.Incomplete texm* sequence.Invalid texm* sequence.Invalid texm* register.First source for cnd instruction must be 'r0.a'.Maximum of 3 cmp instructions allowed.The only valid modifiers for the first source parameter of lrp are: reg (no mod) or 1-reg (complement).Previous writer to the first source register of lrp instruction should apply the saturate destination modifier.  This ensures consistent behaviour across different hardware. Affected components(*) of first source register: %sConst declaration (def) must appear before other instructions.Destination for def instruction must be of the form c# (where # = reg number). In addition there may be no mask (equivalent to full .xyzw, which is fine).Invalid const register num: %d. Max allowed is %d.c%d already def'd in the shader. Dest write mask must be .rgb, or .rgba (all) for dp3.Maximum of 4 dp4 instructions allowed.First arithmetic instruction cannot have co-issue ('+') set; there is no previous arithmetic instruction to pair with.Cannot set co-issue ('+') on a texture instruction.  Co-issue only applies to arithmetic instructions.Cannot set co-issue ('+') on consecutive instructions.(previous instruction) nop instruction cannot be co-issued.nop instruction cannot be co-issued.(previous instruction) dp4 instruction cannot be co-issued.dp4 instruction cannot be co-issued.Co-issued instructions cannot both be dot-product, since each require use of the color/vector pipeline to execute.(previous instruction) Dot-product needs color/vector pipeline to execute, so instruction co-issued with it cannot write to color components.Dot-product which writes alpha cannot co-issue, because both alpha and color/vector pipelines used.Dot-product needs color/vector pipeline to execute, so instruction co-issued with it cannot write to color components.(previous instruction) Dot-product which writes alpha cannot co-issue, because both alpha and color/vector pipelines used by the dot product.(previous instruction) Co-issued instruction cannot write all components - must write either alpha or color.Co-issued instruction cannot write all components - must write either alpha or color.Co-issued instructions cannot both write to the same components of a register.  Affected components: %sCo-issued instructions cannot both write to color components.Co-issued instructions cannot both write to alpha component.Too many texture addressing instruction slots used: %d. Max. allowed is %d. (Note that some texture addressing instructions may use up more than one instruction slot)Too many arithmetic instruction slots used: %d. Max. allowed (counting any co-issued pairs as 1) is %d.Total number of instruction slots used too high: %d. Max. allowed (counting any co-issued pairs as 1) is %d.r0 must be written by shader. Uninitialized component%s(*): %sVersion Token: Shader version %s is not supported by device. Instruction not supported by version %s shader.(Source param) (First source param) (Second source param) (Third source param) %sModifiers are not allowed on constants for ps_1_4.%sSource register type must be texture coordinate input (t#) for texcrd instruction.%sSource register type must be temp (r#) or texture coordinate input (t#) for tex* instruction.%sInvalid register number: %d.  Max allowed for this type is %d._dz(=_db) modifier on source param for texld only allowed if source is a temp register (r#)._dz(=_db) modifier on source param for texld must be paired with source selector .xyz(=.rgb). Note: Using no selector is treated same as .xyz here._dz(=_db) modifier cannot be used on source parameter for texcrd. It is only available to texld instruction, when source parameter is temp register (r#)._dw(=_da) modifier on source param for texld only allowed if source is a texture coordinate register (t#)._dw(=_da) modifier on source param must be paired with source selector .xyw(=.rga).%sInvalid source modifier for tex* instruction.Source for texcrd requires component selector .xyw(==.rga), or .xyz(==.rgb). Note: Using no selector is treated same as .xyz here.Using a texture coordinate register (t#) as source for texld requires component selector .xyw(=.rga), or .xyz(=.rgb). Note: Using no selector is treated same as .xyz here.Using a temp register (r#) as source for texld requires component selector .xyz(==.rgb). Note: Using no selector is treated same as .xyz here.%sInvalid source selector for tex* instruction.Texture coordinate register t%d read more than once in shader with different source selector (swizzle). Multiple reads of identical texture coordinate register throughout shader must all use identical source selector. Note this does not restrict mixing use and non-use of a source modifier (i.e. _dw/_da or _dz/_db, depending what the swizzle allows) on these coordinate register reads.%sTexture coordinate registers (t#) are not available to arithmetic instructions.%sInvalid register type.%sInvalid register number: %d. Max allowed for this type is %d.%sInvalid source modifier.%sInvalid source selector._dz(=_db) modifier may only be used at most 2 times in a shader.Read of uninitialized component%s(*) in %s%d: %s. Note that when texcrd is used with a .xy(==.rg) writemask, as it is in this shader, a side effect is that anything previously written to the z(==b) component of the destination r# register is lost and this component becomes uninitialized. In order to read blue again, write to it first. Also: Note that an unfortunate effect of the phase marker earlier in the shader is that the moment it is encountered in certain hardware, values previously written to alpha in any r# register, including the one noted here, are lost. In order to read alpha from an r# register after the phase marker, write to it first.Read of uninitialized component%s(*) in %s%d: %s. Note that an unfortunate effect of the phase marker earlier in the shader is that the moment it is encountered in certain hardware, values previously written to alpha in any r# register, including the one noted here, are lost. In order to read alpha from an r# register after the phase marker, write to it first.Read of uninitialized component%s(*) in %s%d: %s. Note that when texcrd is used with a .xy(==.rg) writemask, as it is in this shader, a side effect is that anything previously written to the z(==b) component of the destination r# register is lost and this component becomes uninitialized. In order to read blue again, write to it first.The current tex* instruction reads from %c%d, which was written earlier by another tex* instruction in the same block of tex* instructions.  Dependent reads are not permitted within a single block of tex* instructions.  To perform a dependent read, separate texture coordinate derivation from the tex* instruction using the coordinates with a 'phase' marker.Invalid register type for destination param.Invalid destination register number: %d. Max allowed for this register type is %d.texcrd with _dw(=_da) source modifier must use .xy(=.rg) destination writemask.texcrd must use .xyz(=.rgb) destination writemask.texld/texkill/texdepth instructions must write all components.Instruction modifiers not allowed for tex* instructions.Destination shift not allowed for tex* instructions.Invalid instruction modifier.Invalid destination shift.%d different texture coordinate registers (t#) read by instruction.  Max. different texture registers readable per instruction is %d.Register r%d (and thus texture stage %d) already used as a destination for a tex* instruction in this block of the shader. Reuse of a texture stage in ps_1_4 may only be accmplished by splitting the tex* ops across a phase marker.tex* instructions cannot be after arithmetic instructions within one phase of a ps_1_4 shader.  Each phase can have a block of tex* instructions followed by a block of arithmetic instructions. Multiple phase markers not permitted.  Aborting shader validation.Earlier texld instruction used _dz(=_db) modifier on source param. When a phase marker is present, the _dz modifier is only permitted after the phase marker.v# register read by instruction(s) before phase marker.  This is not permitted. When a phase marker is present, v# register reads are only permitted after the phase marker.When a phase marker is present in a shader, texkill is only permitted after the phase marker.bem may only be used once in a shader.bem can only be used before a phase marker (required) later in the shader.Writemask for bem must be '.rg'First source parameter for bem must be temp (r#) or constant (c#) register.Second source parameter for bem must be temp (r#) register.Only one use of texdepth is permitted.Destination for texdepth must be r5.After texdepth instruction, r5 is no longer available in shader.When a phase marker is present in a shader, texdepth is only permitted after the phase marker.Cannot set co-issue ('+') on a tex* instruction.  Co-issue only applies to arithmetic instructions.Phase marker cannot be co-issued.dp4 cannot be coissued.Instruction cannot have co-issue ('+') set without a previous arithmetic instruction to pair with.(previous instruction)%s phase marker cannot be co-issued.%s def cannot be co-issued.%s nop cannot be co-issued.%s dp4 cannot be co-issued.%s bem cannot be co-issued.Co-issued instructions cannot both be dp3, since each require use of the color pipe to execute.(previous instruction) dp3 needs color pipe to execute, so instruction co-issued with it cannot write to color components.dp3 which writes alpha cannot co-issue since it uses up both the alpha and color pipes.(previous instruction) dp3 which writes alpha cannot co-issue since it uses up both the alpha and color pipes.(previous instruction) Individual instruction in co-issue pair cannot write both alpha and color component(s).Individual instruction in co-issue pair cannot write both alpha and color component(s).Co-issued instructions cannot both write to the same component(s).  One instruction must write to alpha and the other may write to any combination of red/green/blue.  Destination registers may differ.One of the instructions in a co-issue pair must write to alpha only (.a writemask).Too many (%d) tex* instruction slots used before phase marker. Max. allowed in a phase is %d.Cannot fit shader into length limits for target shader model (ps_1_4). Too many (%d) arithmetic instruction slots used before phase marker. Max. allowed in a phase (counting any co-issued pairs as 1) is %d.Too many (%d) tex* instruction slots used after phase marker. Max. allowed in a phase is %d.Too many (%d) arithmetic instruction slots used after phase marker. Max. allowed in a phase (counting any co-issued pairs as 1) is %d.Too many (%d) tex* instruction slots used. Max. allowed is %d. Note that adding a phase marker to the shader would double the number of instructions available.Too many (%d) arithmetic instruction slots used. Max. allowed (counting any co-issued pairs as 1) is %d. Note that adding a phase marker to the shader would double the number of instructions available.r0 must be written by shader. Uninitialized component%s(*): %s. Note that when texcrd is used with a .xy(==.rg) writemask, as it is in this shader, a side effect is that anything previously written to the z(==b) component of the destination r# register is lost and this component becomes uninitialized. The blue component of r0 must to be written after the texcrd. Also: Note that an unfortunate effect of the phase marker in the shader is that the moment it is encountered in certain hardware, values previously written to alpha in any r# register, including r0, are lost. So after a phase marker, the alpha component of r0 must be written.r0 must be written by shader. Uninitialized component%s(*): %s. Note that an unfortunate effect of the phase marker in the shader is that the moment it is encountered in certain hardware, values previously written to alpha in any r# register, including r0, are lost. So after a phase marker, the alpha component of r0 must be written.r0 must be written by shader. Uninitialized component%s(*): %s. Note that when texcrd is used with a .xy(==.rg) writemask, as it is in this shader, a side effect is that anything previously written to the z(==b) component of the destination r# register is lost and this component becomes uninitialized. The blue component of r0 must to be written after the texcrd.Version Token: Pixel shader version ps_2_sw is for software rasterizers only (e.g. the reference device). Aborting shader validation.ps_2_x extended instruction not supported by the hardware (static flow control not supported).ps_2_x extended instruction not supported by the hardware (gradient instructions not supported).ps_2_x extended instruction not supported by the hardware (predication not supported).ps_2_x extended instruction not supported by the hardware (dynamic flow control not supported).ps_2_x extended instruction not supported by the hardware (neither predication or static flow control supported).Instruction not supported by version %s pixel shader.%s.a%s.r%s.g%s.b%s.%sr%sg%sb%sa%s/%sw%sx%sy%sz(Fourth source param) First source parameter for texld must be temp (r#) or texture coordinate input(t#) register.First source parameter for texld can't specify min precision unless shader is from D3D10+ target.Unrecognized min precision on source parameter.Second source parameter for texld must be sampler stage (s#).Second source parameter for texld can't specify min precision.Third and fourth parameters to texldd must be temp (r#), texture (t#), input (v#) or constant (c#) register.Third and fourth parameter for texldd can't specify min precision unless shader is from D3D10+ target.Third or fourth parameter for texldd using unrecognized min precision.%sUnexpected source parameter.%sSource modifier not allowed for tex* instruction.%sSource swizzles not allowed on tex* instruction.%s instruction requires parameter to be label (l#). label parameter doesn't allow min precision.breakp requires parameter to be predicate register (p0). predicate parameter doesn't allow min precision.%s requires the first parameter to be a label (l#).  (second)On current device, %s requires the condition%s parameter to be boolean constant register (b#). On current device, %s requires the condition%s parameter to be predicate register (p0). %s requires the condition parameter%s to be boolean constant register (b#), or predicate register (p0). %s requires the condition parameter%s to be boolean constant register (b#). %s condition parameter%s can't specify min precision. rep requires parameter to be integer constant register (i#). rep doesn't allow min precision on parameter.Source parameter can't specify min precision unless shader is from D3D10+ target.%sInvalid source register type for instruction.%sRegister number: %d on this parameter for a matrix instruction causes attempt to access out of range register number %d. Max allowed for this type is %d.Cannot negate second source parameter to vector*matrix instructions.Cannot use negate on source parameter(s) to %s instruction.%s%s requires replicate swizzle for this parameter in order to select component. i.e. .x | .y | .z | .w (or rgba equivalent)Parameter(s) for %s instruction must specify default swizzle (.xyzw, or none specified.).  The exception is (on shader version > ps_2_0) if the condition is the predicate register, p0, in which case a replicate swizzle must be used in order to select a component. i.e. .x | .y | .z | .w (or rgba equivalent) When predicate register is used as the condition for a %s instruction, a replicate swizzle must be specified, to select a component. i.e. .x | .y | .z | .w (or rgba equivalent)Parameter(s) for %s instruction must specify default swizzle (.xyzw, or none specified.) Const bool (b#) parameter to %s instruction must specify default swizzle (.xyzw, or none specified.) Predicate register (p0) parameter to %s instruction must specify replicate swizzle in order to select component. i.e. .x | .y | .z | .w (or rgba equivalent)Cannot swizzle second source parameter to vector*matrix instructions.%sInvalid source selector: %s. The only available source swizzles in this shader version are: .rgba/xyzw (same as not specifying swizzle), .r/x, .g/y, .b/z, .a/w, .gbra/yzxw, .brga/zxyw and .abgr/wzyx. ps_2_0 does not support predication.vs_2_x predication not supported by the hardware.%s instruction cannot be predicated.Source predicate must be p0 register.Source predicate p0 must use one of the following swizzles: .x | .y | .z | .w | .xyzw (same as swizzle not present)The only modifier allowed for source predicate p0 is the not (!) modifier.When writing to oDepth with predication, p0 must use a replicate swizzle to select a single component: .x | .y | .z | .wSampler register s%d has not been declared.Component%s of register %s%d being read, but not declared. v# and t# registers must be declared using a dcl statement (down to the component level) in %s. Undeclared component%s(*) being read: %sr/xg/yb/za/wNote that the %s component of %s%d was previously initialized, but then became uninitialized by a previous instruction (e.g. SINCOS clobbers components).Writemask cannot be empty.Min precision not allowed on predicate register.Dest parameter can't specify min precision unless shader is from D3D10+ target.Unrecognized min precision on dest parameter.texkill must write all components.texld* must not specify a writemask (same as full mask). texld* instructions always write 4 components, including defaults if the source texture being sampled contains fewer than 4 components. Dest writemask for SINCOS must be .xy, .x or .y._sat not permitted on tex* instructions._sat not permitted with frc instruction._sat not permitted with SINCOS instruction._sat not permitted with setp instruction.Instruction modifiers other than _sat or _pp not permitted. (_sat is permitted only on arithmetic ops, except frc or SINCOS)Instruction shifts not permitted.M3x2xyM3x3xyzM3x4xyzw (same as not specifying mask)M4x3M4x4%s instruction must use destination writemask: .%sDest register cannot be the same as first source register for m*x* instructions.Dest register for m*x* instructions cannot be the same as one of the additional registers implied by the second source register.Shader uses texture addressing operations in a dependency chain that is too complex for the target shader model (%s) to handle.  Dependent tex-op sequence too long (%dth order). A 1st order dependent tex-op is a tex[ld*|kill] instruction in which either: (1) an r# reg is input (NOT t# reg), or (2) output r# reg was previously written, now being written AGAIN. A 2nd order dependent tex-op occurs if: a tex-op reads OR WRITES to an r# reg whose contents, BEFORE executing the tex-op, depend (perhaps indirectly) on the outcome of a 1st order dependent tex-op. An (n)th order dependent tex-op derives from an (n-1)th order tex-op. A given tex-op may be dependent to at most 3rd order (ps_2_0/x only).%d different input (v#) or texture (t#) registers read by instruction.  Max. different input/texture registers readable per instruction is %d.%d different constant registers (c#) read by instruction.  Max. different constant registers readable per instruction is %d.(There is one exception: this rule does not apply to the SINCOS macro instruction.)%d constant registers (c#) read by instruction.  Max. constant registers readable per instruction (even if they are the same) is %d.  This is in addition to the read port limit of %d for constants, which restricts how many *different* constants can be read. (There is one exception: none of this applies to the SINCOS macro instruction.)Multiple constant registers cannot be read by a matrix op.Multiple input/texture registers cannot be read by a matrix op.def and dcl instructions must appear before other instructions.dcl instruction is missing a parameter.Invalid register type for dcl.  Must be t#, v# or s#.Invalid register number: %d. Max allowed for %s# register is %d.Min precision not allowed on dest parameter.Register %s%d has already been declared.dcl %s# does not support any modifiers.dcl %s# must have one of the following masks: x, xy, xyz or xyzw (alternatively: r, rg, rgb, or rgba).dcl %s# only supports the _centroid modifier (optional hint), and/or _pp modifier (partial precision hint). No other modifiers supported.dcl %s# must be one of the following types: dcl_2d, dcl_cube or dcl_volume.dcl %s# must not specify a writemask (equivalent to a full mask). When samplers are used for texture lookup, 4 components are always returned, including defaults for components that may not be present in the texture format set at the sampler. dcl %s# does not support any modifiers. dcl must specify non-empty mask.def or dcl instructions must appear before other instructions.Destination for defi instruction must be i# register (where # = reg number). In addition there may be no mask (equivalent to full .xyzw, which is fine).Invalid constant integer (i#) register num: %d. Max allowed is %d.i%d.x (which represents rep iteration count) cannot be negative. i%d.x is currently def'd as %d. i%d.x (which represents rep iteration count) cannot be greater than %d. i%d.x is currently def'd as %d. i%d.yzw have no meaning in this shader model; they must simply be 0. i%d already def'd in the shader. Destination for defb instruction must be b# register (where # = reg number). In addition there may be no mask (equivalent to full .xyzw, which is fine).Invalid constant bool (b#) register num: %d. Max allowed is %d.b%d must only be defined as true (0x00000001) or false (0x00000000). b%d already def'd in the shader. Src and dest registers for NRM cannot be the same.Dest writemask for NRM must be .xyzw (default) or .xyz (or equivalent rgba notation)Dest register for CRS cannot be the same as a source register.Swizzle not permitted on source parameters to CRS.Write mask for CRS must be one of: .x | .y | .z | .xy | .xz | .yz | .xyz (or rgba equivalent)Dest register for POW cannot be the same as second source register.Dest register for LRP cannot be the same as first or third source register.Dest register for SINCOS cannot be the same as first source register.Second source parameter for SINCOS must be a constant register.Third source parameter for SINCOS must be a constant register.Second and third source parameters for SINCOS cannot be the same constant register.Source selector for first source parameter for SINCOS must be .x, .y, .z or .w.Second and third source parameters for SINCOS cannot have a modifier.Second and third source parameters for SINCOS must use default swizzle (no swizzle specified, or .xyzw). Third source parameter for dp2add must use a replicate swizzle (.r, .g, .b, .a) to select a scalar component.Co-issue ('+') is not supported in this shader version.Pixel shader must minimally write to oC0 (with a mov instruction).When a %s shader writes to oCn, it must write to all of oC(n-1) down to oC0 (no gaps).oCn registers may only be written using the mov instruction.Source parameter for instruction writing to oCn cannot use a modifier.Source parameter for instruction writing to oCn cannot use swizzles.Write to oCn register cannot use _sat instruction modifier.Write to oCn register must use full writemask (equivalent to not specifying writemask at all).oC%d already written. (oCn registers can only be written at most once each)oDepth may only be written using the mov instruction.Source parameter for instruction writing to oDepth cannot use a modifier.Source parameter for instruction writing to oDepth must use a replicate source swizzle. i.e.: .x | .y | .z | .w or .r | .g | .b | .a.  This identifies the scalar component of the source to send to oDepth.Write to oDepth register cannot use _sat instruction modifier.Write to oDepth register must not specify any writemask. (Note, this is equivalent to using a full writemask) oDepth is a scalar output, however a specific rgba/xyzw channel does not apply; the writemask is meaningless. oDepth already written.Subroutine with label #%d called, but never defined.Subroutine label #%d never referenced.End of shader reached without 'ret' to terminate subroutine.End of shader reached and rep construct was not completed with an endrep. End of shader reached and 'if' construct was not completed with 'else'/'endif'. Subroutine label number, %d, is too large. Maximum label number is %d. Aborting shader validation.Subroutine label number: %d already defined earlier. Aborting shader validation.Cannot call subroutine label defined earlier in shader (label #%d in this case).  Subroutine call must reference label defined later in shader. Aborting shader validation. 'label' is only permitted directly after a 'ret' instruction. Aborting shader validation. Label is defined inside a subroutine or main program. Label must follow the ret instruction. Aborting shader validation. Compiled code results in dynamic flow control nesting depth that exceeds limit of %d for target (%s). Depth of dynamic 'if' nesting exceeds limit of %d (callnz with predicate counts as a dynamic 'if' nesting level). Aborting shader validation. Compiled code results in subroutine call nesting depth that exceeds limit of %d for target (%s). Depth of subroutine call nesting exceeds limit of %d. Aborting shader validation. Out of memory. Aborting shader validation. 'ret' instruction not permitted from inside any flow control block. Aborting shader validation. Compiled code results in loop nesting depth that exceeds limit of %d for target (%s). Depth of loop nesting exceeds limit of %d. Aborting shader validation. 'endrep' instruction does not match up to a 'rep'. Aborting shader validation. Compiled code results in dynamic 'if'/'endif' nesting depth that exceeds limit of %d for target (%s). Depth of dynamic 'if' nesting exceeds limit of %d. Aborting shader validation. Compiled code results in static 'if'/'endif' nesting depth that exceeds limit of %d for target (%s). Depth of static 'if' nesting exceeds limit of %d. Aborting shader validation. 'endif' instruction does not match up to an 'if' or 'else'. Aborting shader validation. 'else' instruction does not match up to an 'if'. Aborting shader validation. 'else' already used for current 'if' construct. Aborting shader validation. Compiled code results in dynamic 'if'/'endif' nesting depth that exceeds limit of %d for target (%s) (due to conditional break that counts towards the same limit). Depth of dynamic 'if' nesting exceeds limit of %d, due to break_cmp that counts towards same limit. Aborting shader validation. 'break' instruction not within a local rep/endrep construct. Aborting shader validation. A 'ret' instruction must be followed by either (1) the end of the shader or (2) a 'label' instruction. Aborting shader validation.texld/texldb/texldp/dsx/dsy instructions with r# as source cannot be used inside dynamic conditional 'if' blocks, dynamic conditional subroutine calls, or rep with break*. Compiled shader code has has many operations that use the texture unit (%d). Max. allowed by the target (%s) is %d.Too many (%d) tex* instruction slots used. Max. allowed is %d.Compiled shader code uses too many arithmetic instruction slots (%d). Max. allowed by the target (%s) is %d. Consider increasing optimization level to reduce instruction count.Too many (%d) standard (non tex*) instruction slots used. Max. allowed is %d.Compiled shader code uses too many instruction slots (%d). Max. allowed by the target (%s) is %d.Too many (%d) total instruction slots used. Max. allowed is %d.break_cmpcommentendif_cmptexld[b|p]*texcoord/texcrdVersion Token: Pixel shader version ps_3_sw is for use with software rasterizers only (e.g. the reference device). Aborting shader validation.fourth%s requires %s parameter to be label (l#). %s requires second source parameter (the condition) to be boolean constant register (b#), or predicate register (p0). loop requires first parameter to be loop counter (aL). %s requires %s parameter to be integer constant register (i#). %s requires parameter (the branch condition) to be boolean constant register (b#), or predicate register (p0). First source parameter for texld* must be temp (r#), input (v#) or constant (c#) register.Source modifier not allowed on sampler (s#) parameter to texld* instruction.Second source parameter for texld* must be sampler stage (s#).Third and fourth parameters to texldd must be temp (r#), input (v#) or constant (c#) register.Unexpected source parameter.(%s source param) Invalid register number: %d.  Max allowed for this type is %d.(%s source param) Negate or abs modifiers not permitted on source parameters to texld*Invalid reg num for MISCTYPE.Relative addressing only permitted on input (v#) registers (%s source param).Relative address register must be aL register (%s source param).Invalid register number, %d, specified for aL register. Max # supported is %d (%s source param).vFace or vPos registers cannot be used as sources for matrix operations.Reg num: %d for %s source param on matrix instruction causes attempt to access out of range register number %d. Max allowed for this type is %d.Cannot use abs on source parameter(s) on to vFace register.Cannot use negate or abs on second source parameter to vector*matrix instructions.Cannot use negate or abs on source parameter(s) to %s instruction.vFace register must not specify a swizzle (i.e. default swizzle), as it is an implied scalar.vFace register can only be used as one of the sources to if_(cond), break_(cond), setp_(cond), or the condition in a cmp.%s requires replicate swizzle for source parameter(s) in order to select component. For the vPos register, this can either be .x or .y (z,w are not available). %s requires replicate swizzle for source parameter(s) in order to select component. i.e. .x | .y | .z | .w (or rgba equivalent)Parameter(s) for %s instruction must specify default swizzle (.xyzw, or none specified.).  The exception is if the condition is the predicate register, p0, in which case a replicate swizzle must be used in order to select a component. i.e. .x | .y | .z | .w (or rgba equivalent)aL can only be referenced in the following scenarios: (1) inside a loop/endloop block, or (2) in a subroutine for which in all cases some call below in the stack is in a loop/endloop block. Component%s of register %s%d being read, but not declared. v# registers must be declared using dcl statement(s) (down to the component level). Affected components (*): %sComponent(s) of register vPos being read, but not declared. vPos must be declared using a dcl statement. Affected components (*): %svPos does not have .z or .w channels in this shader model. Attempt to read following unavailable component(s) (*): %svFace being read, but not declared. vFace must be declared if it is used:  dcl vFace_centroid flag only permitted on dcl v# statements.The only instruction allowed to write to the predicate register is setp.The setp instruction must write to the predicate register.Absolute and relative addressing of input registers cannot be combined in one instruction.Different relative addressing of input registers cannot be combined in one instruction.When constant registers are read multiple times in a single instruction, the _abs modifier must either be present on all of the constants, or none of them. %d different input registers (v*#) read by instruction.  Max. different input registers readable per instruction is %d.Multiple input registers cannot be read by a matrix op.Invalid register type for dcl.  Must be input register (v#), sampler (s#), position (vPos) or face (vFace).dcl can't specify empty writemask.dcl for %s register does not support any modifiers. dcl %s# only supports the (optional) _pp modifier (partial precision hint), and/or the _centroid modifier (relevant to multisampling). No other modifiers supported.Sampler %s%d already declared. dcl %s# must not specify a writemask (equivalent to a full mask). Declaration for register %s%d overlaps previous declaration for the following component(s) of the same register (*): %sUnrecognized usage type in dcl statement.dcl usage index, %d, is too high.  Max allowed is %d.When multple usages are declared for various components of a given input v# register, the _centroid hint can only be specified on either (a) all usages declared for the register, or (b) on none of them.  Also note that the usage 'color' (with any index) has special behavior: even if the centroid hint is not specified for color, it is assumed to be set. dcl usage+index psize0 cannot be used in a pixel shader.dcl for input v# register must specify usage+index (semantic). i.e. dcl_texcoord5 v%d. Note that the semantics position0, positiont0, psize0, tessfactor(n) and sample(n) are not permitted.dcl usage+index positiont0 cannot be used in a pixel shader.dcl usage 'tessfactor' is not avaliable to the pixel shader. dcl usage 'sample' is not avaliable to the pixel shader. dcl usage+index: %s,%d has already been specified for an input register.%s register already declared.z or w components of vPos register are not available in this shader version, and cannot be dcl'd.i%d.x (which represents loop or rep iteration count) cannot be negative. i%d.x is currently def'd as %d. i%d.x (which represents loop or rep iteration count) cannot be greater than %d. i%d.x is currently def'd as %d. i%d.y (which represents loop initial value) must be in the range [0, %d]. i%d.y is currently def'd as %d. i%d.z (which represents loop step value) must be in the range [-%d, %d]. i%d.z is currently def'd as %d. i%d.w has no meaning; it must simply be 0. Swizzle not permitted on source paramters to CRS.Dest for SINCOS must be a temp (r#) register.oDepth may not be written by the %s instruction.When writing to oDepth, %s instruction must use replicate swizzle on source parameter(s), in order to select single component. i.e. .x | .y | .z | .w (or rgba equivalent)Write to oDepth register must not specify any writemask. (Note, this is equivalent to using a full writemask) oDepth is a scalar output, however a specific rgba/xyzw channel does not apply -> the writemask is meaningless. End of shader reached and '%s' construct was not completed with a '%s'. 'endloop' instruction does not match up to an 'loop'. Aborting shader validation. 'break' instruction not within a local loop/rep construct. Aborting shader validation. texld/texldb/texldp/dsx/dsy instructions with r# as source cannot be used inside dynamic conditional 'if' blocks, dynamic conditional subroutine calls, or loop/rep with break*. Too many instruction slots (%d) used by shader. Max. allowed is %d.Version token: 0x%x indicates a pixel shader.  Vertex shader version token must be of the form 0xfffe****.Version Token: 0x%x is invalid. Vertex shader version token must be of the form 0xfffe****. Aborting vertex shader validation.vs_1_0 is no longer supported.  It turned out that vertex shader capable hardware will always support at least vs_1_1 (which is not as limited a model as vs_1_0 was). To convert a vs_1_0 shader up to vs_1_1, the only change needed is to make the version number 1_1. Version Token: Shader version %s is not supported. Aborting vertex shader validation.%s requires replicate swizzle for the source parameter in order to select component. i.e. .x | .y | .z | .w (or rgba equivalent)Address mode must be absolute (%s source param).Relative addressing of constant register must reference a0.x only.Format for address register must be a0.x.Only the mov instruction is allowed to write to the address register.Dst modifiers not allowed for vertex shaders.Dest shifts not allowed for vertex shaders.Dest write mask cannot be empty.%s instruction cannot write to scalar output registers (oFog, oPts).M*x* matrix instructions cannot write to scalar output registers (oFog, oPts).When writing to scalar output register, %s instruction must use replicate swizzle on source parameter(s), in order to select single component. i.e. .x | .y | .z | .w (or rgba equivalent)Scalar output registers (oFog, oPts) must have full write mask.The only valid write masks for the FRC instruction are .xy and .y.Absolute and relative addressing of constant registers cannot be combined in one instruction.Different relative addressing of constant registers cannot be combined in one instruction.Number of instruction slots used too high: %d. Max. allowed is %d.By the end of a vertex shader, any oTn register written must not have gaps in components, starting from x, in order xyzw. To satisfy this, oT%d requires writing of the additional component%s(*): %s Vertex shader must write all four components (xyzw) of oPos output register.Vertex shader must minimally write all four components (xyzw) of oPos output register.  Missing component%s(*): %sVersion Token: Vertex shader version vs_2_sw is for software use only. Aborting shader validation.vs_2_x extended instruction not supported by the hardware (dynamic flow control not supported).vs_2_x extended instruction not supported by the hardware (predication not supported).vs_2_0 does not support predication.Predicate register read, but uninitialized. Note that the predicate register must be written by setp before it is used, and that flow control instructions invalidate the predicate register's contents. Affected components(*): %sWhen writing to scalar output (oFog, oPts) with predication, p0 must use a replicate swizzle to select a single component: .x | .y | .z | .wpredicate doesn't allow min precision.%s requires second source parameter (the condition) to be boolean constant register (b#). loop doesn't allow min precision on parameters.loop/rep don't allow min precision on parameters.%s requires parameter (the branch condition) to be boolean constant register (b#). %s condition parameter can't specify min precision. Relative addressing only permitted on constant registers (%s source param).Relative address register must be a# register or aL register (%s source param).Invalid register number, %d, specified for a# (address) register. Max # supported is %d (%s source param).Cannot use negate on second source parameter to vector*matrix instructions.Parameter(s) for %s instruction must specify default swizzle (.xyzw, or none specified.).  The exception is (on shader version > vs_2_0) if the condition is the predicate register, p0, in which case a replicate swizzle must be used in order to select a component. i.e. .x | .y | .z | .w (or rgba equivalent) Input register v%d was not declared with a dcl statement.  Attempt to read component%s(*): %sOnly the mova instruction is allowed to write to the address register.mova instruction can only write to the address register.Relative addressing of destination not permitted on destination in this shader model.Min precision not allowed on predicate/loop/addr register.Destination for def instruction must be c# register (where # = reg number). In addition there may be no mask (equivalent to full .xyzw, which is fine).Dest register type for NRM must be temp (r#).Dest register type for CRS must be temp (r#).Dest register type for POW must be temp (r#).Dest register type for LRP must be temp (r#).Second and third source params for SGN must both be different temp (r#) registers.First source param for SGN cannot be the same register as the second or third params.Second and third source params for SGN cannot use a source selector, and cannot have a modifier. Second source paramter for SINCOS must be a constant register.Third source paramter for SINCOS must be a constant register.Dest register type for SINCOS must be temp (r#).Dest mask for SINCOS must be one of: .x | .y | .xy More than 2 constants (even identical ones) cannot be read by an instruction. (There is one exception: this rule does not apply to the SINCOS instruction.)%d different input registers (v#) read by instruction.  Max. different input registers readable per instruction is %d. %d different constant registers (c#) read by instruction.  Max. different constant registers readable per instruction is %d. (There is one exception: this rule does not apply to the SINCOS instruction.)Shader has too much flow control complexity for the target (%s). Too may static flow control instructions (%d) for this shader model.  Maximum allowed is %d. The shader instructions that count as 1 static flow control instruction each are: (1)call, (2)callnz (with static condition), (3)if (static branch), (4)else (paired with static if), (5)loop, (6)rep. Compiled code results in subroutine nesting depth that exceeds limit of %d for target (%s). Version Token: Vertex shader version vs_3_sw is for software use only. Aborting shader validation.Version Token: Shader version %s is not supported. Aborting vertex shader validation. Too many output registers declared (%d).  When no output register has been declared with the semantic 'psize0', %d o# registers are available.  When an o# register has been declared with the semantic 'psize0' (same as 'psize'), %d registers are available.Invalid register type for dcl.  Must be input register (v#), output register (o#) or sampler (s#).dcl usage 'tessfactor' is not permitted for vertex shader input registers.Input cannot be dcl'd with usage+index positiont0, as vertex data containing this semantic has special meaning to the API: skip vertex processing altogether.Vertex shader output is not permitted to be dcl'd with the usage+index positiont0.Vertex shader output dcl with usage 'tessfactor' must have usage index 0, and register must have .x write mask. This semantic is for special purpose use only: creating vertex data that is to be used with tesselation, where a scalar tessfactor is needed.  If you are not doing tesselation, do not bother using this semantic. Output register dcl'd with usage+index psize0 takes as special meaning as a scalar, so no writemask must be specified (identical to full write mask). In addition, no other semantics may declared for the same output register as one assigned to psize0. Output register cannot be dcl'd with usage 'sample'.dcl usage+index: %s,%d has already been specified for an output register.Instruction not supported by this vertex shader version.When writing to scalar output (psize) with predication, p0 must use a replicate swizzle to select a single component: .x | .y | .z | .wFirst source parameter for texldl must be temp (r#), input (v#) or const (c#) register.(%s source param) Source modifier not allowed on texcoord for texldl.(%s source param) Source modifier not allowed on sampler (s#).Second source parameter for texldl must be sampler stage (s#).Relative addressing of source register only permitted on input (v#) and constant (c#) registers (%s source param).Relative address register for constant (c#) must be a# register or aL register (%s source param).Relative address for input (v#) can only be aL register (%s source param).Attempt to read undeclared component%s of input register v%d (*): %s. Components of v# registers to be read must be declared by a dcl statement.%s instruction does not support _sat modifier.Invalid dst modifier for vertex shader.Relative addressing of destination only permitted on output registers (o#).Relative addressing of o# register requires aL register.When relative addressing of output o# registers is used, position0 must be declared in o%d only, psize0 (if present) must be declared in o%d only, and indexing from/into o%d, or o%d (psize0 case only) is undefined. Indexing into any other declared o# is fine. If relative addressing of o# is not used in the shader, these restrictions on register numbers do not apply. %s instruction cannot write to scalar output register.M*x* matrix instructions cannot write to scalar output register.Scalar output register must have full write mask.Attempt to write undeclared component%s of output register o%d (*): %s. Components of o# registers to be written must be declared by a dcl statement.%d different constant registers (c#) read by instruction.  Max. different constant registers readable per instruction is %d. Compiled shader code uses too many instruction slots (%d). Max. allowed by the target (%s), including cap for instruction limit, is %d.Compiled shader code uses too many instructions (%d). Max. allowed by the target (%s), including cap for instruction limit, is %d.Reserved bit(s) set in instruction parameter token!  Aborting validation.dcl instruction should have exactly 2 parameter tokens.  Aborting validation.Bit 31 not set in dcl info token!  Aborting validation.Reserved bit(s) set in destination parameter token!  Aborting validation.Reserved bit(s) set in dcl info token!  Aborting validation.Reserved bit(s) set in source %d parameter token!  Aborting validation.Expected relative address token.  Aborting validation.Reserved bit(s) set in relative address token for source parameter %d!  Aborting validation.When aL is used as a relative address, it must not specify any swizzle, as it is a scalar register. Aborting validation.Instruction length specified for instruction (%d) does not match the token count encountered (%d). Aborting validation.Unexpected DWORD count for instruction.  Aborting validation.Unrecognized instruction. Aborting pixel shader validation.Unrecognized instruction. Aborting vertex shader validation.Invalid register type for dcl.  Must be input register (v#).dcl must specify full writemask in this shader version (same as not specifying mask) for %s# registers.dcl usage 'tessfactor' is not permitted for vertex input shaders.dcl usage: %s%d has already been specified.Relative address must specify a single component selector (.x, .y, .z or .w) to indicate relative address component. Aborting validation.Reserved bit(s) set in parameter %d source token!  Aborting validation.D3DSerializeRootSignature: unsupported root signature version (%u)
Descriptor range (descriptor table slot [%u], root parameter [%u]) overlaps with another incompatible descriptor range.
Unsupported RangeType value %u (descriptor table slot [%u], root parameter [%u]).
Samplers cannot be mixed with other resource types in a descriptor table (root parameter [%u]).
NumDescriptors cannot be 0 (descriptor table slot [%u], root parameter [%u]).
Cannot append range with implicit lower bound after an unbounded range (descriptor table slot [%u], root parameter [%u]).
Overflow for shader register range: BaseShaderRegister=%u, NumDescriptor=%u; (descriptor table slot [%u], root parameter [%u]).
Overflow for descriptor range (descriptor table slot [%u], root parameter [%u])
VERTEXHULLDOMAINGEOMETRYPIXELAMPLIFICATIONMESHRoot parameter [%u] descriptor table entry [%u] specifies RegisterSpace=%#x, which is invalid since RegisterSpace values in the range [%#x,%#x] are reserved for system use.
Root parameter [%u] specifies RegisterSpace=%#x, which is invalid since RegisterSpace values in the range [%#x,%#x] are reserved for system use.
(root parameter [%u], visibility %s, descriptor table slot [%u])(root parameter [%u], visibility %s)(static sampler [%u], visibility %s)(root parameter[%u], visibility %s, descriptor table slot [%u])Shader register range of type %s %s overlaps with another shader register range %s.
Unsupported bit-flag set (root signature flags %x).
D3D12_ROOT_SIGNATURE_FLAG_LOCAL_ROOT_SIGNATURE combined with other flag(s) that don't make sense (root signature flags %x).
D3D12_ROOT_SIGNATURE_FLAG_LOCAL_ROOT_SIGNATURE not supported if device does not support raytracing or work graphs (root signature flags %x).
Unsupported ShaderVisibility value %u (root parameter [%u]).
Local root signatures only support shader visibility flag D3D12_SHADER_VISIBILITY_ALL.  ShaderVisibility value: %u (root parameter [%u]).
Unsupported bit-flag set (descriptor range flags %x).
Descriptor range flags cannot specify more than one DESCRIPTOR_* flag at a time (descriptor range flags %x).
Sampler descriptor ranges can't specify DATA_* flags since there is no data pointed to by samplers (descriptor range flags %x).
Sampler descriptor ranges can't specify DESCRIPTORS_STATIC_KEEPING_BUFFER_BOUNDS_CHECKS, since there are no bounds to check (descriptor range flags %x).
Descriptor range flags cannot specify more than one DATA_* flag at a time (descriptor range flags %x).
Descriptor range flags cannot specify DESCRIPTORS_VOLATILE with the DATA_STATIC flag at the same time (descriptor range flags %x). DATA_STATIC_WHILE_SET_AT_EXECUTE is fine to combine with DESCRIPTORS_VOLATILE, since DESCRIPTORS_VOLATILE still requires descriptors don't change during execution. 
Root constants Num32BitValues should be > 0.
Unsupported bit-flag set (root descriptor flags %x).
Root descriptor flags cannot specify more than one DATA_* flag at a time (root descriptor flags %x).
Unsupported ParameterType value %u (root parameter %u)
Unsupported ShaderVisibility value %u (static sampler [%u]).
Local root signatures only support shader visibility flag D3D12_SHADER_VISIBILITY_ALL.  ShaderVisibility value: %u (static sampler [%u]).
Shader sampler descriptor range (BaseShaderRegister=%u, NumDescriptors=%u, RegisterSpace=%u) is not fully bound in root signature
A Shader is declaring a resource object as a texture using a register mapped to a root descriptor SRV (ShaderRegister=%u, RegisterSpace=%u).  SRV or UAV root descriptors can only be Raw or Structured buffers.
Shader SRV descriptor range (BaseShaderRegister=%u, NumDescriptors=%u, RegisterSpace=%u) is not fully bound in root signature
A Shader is declaring a typed UAV using a register mapped to a root descriptor UAV (ShaderRegister=%u, RegisterSpace=%u).  SRV or UAV root descriptors can only be Raw or Structured buffers.A Shader is declaring a structured UAV with counter using a register mapped to a root descriptor UAV (ShaderRegister=%u, RegisterSpace=%u).  SRV or UAV root descriptors can only be Raw or Structured buffers.Shader UAV descriptor range (BaseShaderRegister=%u, NumDescriptors=%u, RegisterSpace=%u) is not fully bound in root signatureShader CBV descriptor range (BaseShaderRegister=%u, NumDescriptors=%u, RegisterSpace=%u) is not fully bound in root signature
Shader CBV descriptor range (BaseShaderRegister=%u, NumDescriptors=%u, RegisterSpace%u) is bound to a root constants parameter where Num32BitValues == 0. This root parameter cannot provide data to the CBV, and therefore this buffer is considered not bound.
Shader has root bindings but root signature uses a DENY flag to disallow root binding access to the shader stage.
Static sampler: A NULL pSamplerDesc was specified.Static sampler: MINIMUM or MAXIMUM filters not supported by the device. To see if the device supports this call CheckFeatureSupport with D3D12_FEATURE_D3D12_OPTIONS and check for TiledResourcesTier support of Tier 2+.Static sampler: Filter unrecognized.Static sampler: AddressU unrecognized.Static sampler: AddressV unrecognized.Static sampler: AddressW unrecognized.Static sampler: MipLODBias must be in the range [%f to %f].  %f specified.Static sampler: MaxAnisotropy must be in the range [%d to %d].  %d specified.Static sampler: ComparisonFunc unrecognized.Static sampler: MinLOD be in the range [-INF to +INF].  %f specified.MaxLOD be in the range [-INF to +INF].  %f specified.Sampler flags contain invalid value. See D3D12_SAMPLER_FLAGS.Sampler flags cannot be used on a device that does not support at least shader model 6.7.Border color is invalid, see D3D12_STATIC_BORDER_COLOR for valid valuesFloating point border color is invalid when D3D12_SAMPLER_FLAG_UINT_BORDER_COLOR is specified. *_UINT border colors can still be used without this flag in static samplers, but if specified, then a *_UINT color must be set.This device does not support non-normalized coordinate sampling.Filter is invalid with non-normalized coordinate sampling. MIN and MAG must be equal, MIP must be point, and Filter cannot be comparison or anisotropy.MinLOD, MaxLOD, and MipLODBias must be 0 when sampling with non-normalized coordinates.AddressU is invalid with non-normalized coordinate sampling. AddressU and AddressV must be either CLAMP or BORDER.AddressV is invalid with non-normalized coordinate sampling. AddressU and AddressV must be either CLAMP or BORDER.D3DSerializeRootSignature: unknown root parameter type (%u)
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